• Journal of Korean Society for Geospatial Information Science
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• v.17 no.4
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• pp.105-112
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• 2009

The present serial cadastral maps, which have lots of problems arisen from map matching processes, have very limited applications. That is, the poor quality of serial cadastral maps has kept us from using them. Therefore, a special project for improving the quality of serial cadastral maps was proposed by korean cadastral specialists to solve those problems. The primary purpose of this study is to provide effective ways of serial cadastral map production by reviewing the errors of the present situation-based serial cadastral map production using GIS and digital orthophoto.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Journal of Information Processing Systems
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• v.16 no.1
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• pp.224-237
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• 2020

Recognition of banknote serial number is one of the important functions for intelligent banknote counter implementation and can be used for various purposes. However, the previous character recognition method is limited to use due to the font type of the banknote serial number, the variation problem by the solid status, and the recognition speed issue. In this paper, we propose an aspect ratio based character region segmentation and a convolutional neural network (CNN) based banknote serial number recognition method. In order to detect the character region, the character area is determined based on the aspect ratio of each character in the serial number candidate area after the banknote area detection and de-skewing process is performed. Then, we designed and compared four types of CNN models and determined the best model for serial number recognition. Experimental results showed that the recognition accuracy of each character was 99.85%. In addition, it was confirmed that the recognition performance is improved as a result of performing data augmentation. The banknote used in the experiment is Indian rupee, which is badly soiled and the font of characters is unusual, therefore it can be regarded to have good performance. Recognition speed was also enough to run in real time on a device that counts 800 banknotes per minute.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.4
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• pp.97-102
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• 2007

In this paper, a new architecture for fast-serial $GF(2^m)$ multiplier with low hardware complexity is proposed. The fast-serial multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the fast-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But The traditional fast-serial architecture needs extra (t-1)m registers for achieving the t times speed. In this paper a new fast-serial multiplier without increasing the number of registers is presented.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.160-167
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• 2005

Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.406-410
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• 1990

This paper presents an approximate analysis of the serial production lines using decomposition technique. A serial production line consists of a series of unreliable machines separated by finite buffers. The serial production line is evaluated by approximation method, the results of which are compared with those examined by the discrete time event simulation, based on this approximation method, a gradient technique is proposed, which improves the efficiency of an operation of production line through the re-allocation of buffers.

• Archives of Plastic Surgery
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• v.47 no.6
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• pp.551-558
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• 2020

Background Giant congenital melanocytic nevus (GCMN) is a rare disease, for which complete surgical resection is recommended. However, the size of the lesions presents problems for the management of the condition. The most popular approach is to use a tissue expander; however, single-stage expansion in reconstructive surgery for GCMN cannot always address the entire defect. Few reports have compared tissue expansion techniques. The present study compared single and serial expansion to analyze the risk factors for complications and the surgical outcomes of the two techniques. Methods We retrospectively reviewed the medical charts of patients who underwent tissue expander reconstruction between March 2011 and July 2019. Serial expansion was indicated in cases of anatomically obvious defects after the first expansion, limited skin expansion with two more expander insertions, or capsular contracture after removal of the first expander. Results Fifty-five patients (88 cases) were analyzed, of whom 31 underwent serial expansion. The number of expanders inserted was higher in the serial-expansion group (P<0.001). The back and lower extremities were the most common locations for single and serial expansion, respectively (P =0.043). Multivariate analysis showed that sex (odds ratio [OR], 0.257; P=0.015), expander size (OR, 1.016; P=0.015), and inflation volume (OR, 0.987; P=0.015) were risk factors for complications. Conclusions Serial expansion is a good option for GCMN management. We demonstrated that large-sized expanders and large inflation volumes can lead to complications, and therefore require risk-reducing strategies. Nonetheless, serial expansion with proper management is appropriate for certain patients and can provide aesthetically satisfactory outcomes.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.6
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• pp.21-27
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• 2015

We analyze the problem that is occurring when using parity mode transformation required for 9 bit serial communication under Linux environment and propose the solution. The parity mode change is used for 9 bit serial communication in the Linux that by nature supports only 8 bit serial communication. delay (around OS tick) arises. Our analysis shows that the cause is minimum length of waiting time to transmit data remained in Tx FIFO buffers. A modified Linux serial driver proposed in this paper decreases the delay less than 1ms by using accurate time delaying. Despite various system communication interfaces, enormous existing standards and system have adopted RS-232 serial communication, and the part of them have communicated by 9bit serial.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.328-332
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• 2006

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.140-143
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• 2000

소형화와 안전성에서 보다 더 진보된 ECC( Elliptic Curve Cryptography) 암호화 알고리즘의 하드웨어적 구현을 제안한다. Basis는 VLSI 구현에 적합한 standard basis이며 m=193 ECC 승산기 회로를 설계하였다. Bit-Parallel 구조를 바탕으로 Digit-Serial/Bit-Parallel 방법으로 구현하였다. 제안된 구조는 VHDL 및 SYNOPSYS로 검증되었다.