• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.67-75
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• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1559-1562
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• 2002

This paper describes a 0.13um ultra-high speed 1Mb CMOS SRAM macro with 1.7ns access time. It achieves ultra-high speed operation using two novel approaches. First, it uses process insensitive sense amplifier (Double-Equalized Sense Amplifier) which improves voltage offset by about 10 percent. Secondly, it uses new replica-based sense amplifier driver which improves bit- line evaluation time by about 10 percent compared to the conventional technique. The various memory macros can be generated automatically by using a compiler, word-bit size from 64kb to 1 Mb including repairable redundancy circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.1-9
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• 2009

In this paper proposed a new method which adaptively eliminates comparator offsets using the threshold voltage shift by the Fowler-Nordheim stress. The method evaluates the sign of comparator offset and gives the FN stress to the stronger MOSFETs of the comparator, leading to offset reduction. We have used an appropriate stressing operation, named 'stress-packet', in order to converge the offset value to zero. We applied the method to the latch-type comparator which is prevalently used for DRAM bitline sense amplifier, and verified through experiments that offsets of the latch-type comparators are nearly eliminated with the stress-packet operations. We also discuss about the reliability issues that must be guaranteed for field application of this method.