• 산업공학
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• 제22권3호
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• pp.252-262
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• 2009

It is crucial to prevent low yields in the semiconductor industry. Since many factors affect variation in yield and they are deeply related, preventing low yield is difficult. There have been substantial researches in the field of yield prediction. Many researchers had used the statistical methods. Many studies have shown that artificial neural network (ANN) achieved better performance than traditional statistical methods. However, despite ANN's superior performance some problems such as over-fitting and poor explanatory power arise. In order to overcome these limitations, a relatively new machine learning technique, support vector machine (SVM), is introduced to classify the yield. SVM is simple enough to be analyzed mathematically, and it leads to high performances in practical applications. This study presents a new efficient classification methodology, Stepwise-SVM (SSVM), for detecting high and low yields. SSVM is step-by-step adjustment of parameters to be precisely the classification for actual high and low yield lot. The objective of this paper is to examine the feasibility of SVM and SSVM in the yield classification. The experimental results show that SVM and SSVM provides a promising alternative to yield classification for the field data.

• Journal of Information Technology Applications and Management
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• 제15권1호
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• pp.243-260
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• 2008

To prevent low yields in the semiconductor industry is crucial to the success of that industry. However, to prevent low yields is difficult because of too many factors to affect yield variation and their complex relation in the semiconductor manufacturing process. This study presents a new efficient detection methodology for detecting abnormal yields including high and low yields, which can forecast the yield level of a production unit (namely a lot) based on yield-related feature variables' behaviors. In the methodology, we use C5.0 to identify the yield-related feature variables that are the combination of correlated process variables associated with yield, use SOM (Self-Organizing Map) neural networks to extract and classify significant patterns of past abnormal yield lots and finally use C5.0 to generate classification rules for detecting abnormal yield lot. We illustrate the effectiveness of our methodology using a semiconductor manufacturing company's field data.

• 대한산업공학회지
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• 제41권6호
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• pp.572-578
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• 2015

Yield prediction is one of the most important issues in semiconductor manufacturing. Especially, for a fast-changing environment of the semiconductor industry, accurate and reliable prediction techniques are required. In this study, we propose a prediction model to predict wafer yield based on virtual metrology process parameters in semiconductor manufacturing. The proposed prediction model addresses imbalance problems frequently encountered in semiconductor processes so as to construct reliable prediction model. The effectiveness and applicability of the proposed procedure was demonstrated through a real data from a leading semiconductor industry in South Korea.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.703-706
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• 2003

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.

• 한국시뮬레이션학회논문지
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• 제14권1호
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• 산업공학
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• 제22권2호
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• pp.126-134
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• 2009

As product quality and yield are essential factors in semiconductor manufacturing, monitoring the main manufacturing steps is a critical task. For the purpose, FDC(Fault detection and classification) is used for diagnosing fault states in the processes by monitoring data stream collected by equipment sensors. This paper proposes an FDC model based on decision tree which provides if-then classification rules for causal analysis of the processing results. Unlike previous decision tree approaches, we reflect the structural aspect of the data stream to FDC. For this, we segment the data stream into multiple subregions, define structural features for each subregion, and select the features which have high relevance to results of the process and low redundancy to other features. As the result, we can construct simple, but highly accurate FDC model. Experiments using the data stream collected from etching process show that the proposed method is able to classify normal/abnormal states with high accuracy.

• 지능정보연구
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• 제9권1호
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• pp.157-177
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• 2003

본 논문은 반도체 FAB공정의 수율개선 및 예측을 위해 데이터마이닝 기법을 적용한 사례를 소개한다. FAB 공정의 복잡성과 생산현장에서 수집되는 방대한 기술데이터로 인해 기존의 통계적 방법이나 엔지니어의 경험적 분석 방법만으로는 미처 파악하지 못하는 수율 저하 요인이 상당 수 존재한다. 본 논문은 먼저, FAB공정을 마친 웨이퍼에 불량 칩(chip)이 지리적으로 특정 위치에 집중적으로 발생하는 현상을 육안검사 대신 군집분석을 이용하여 데이터로부터 자동 판별할 수 있는 방법을 제안한다. 다음으로 연속패턴분석, 분류분석, RBF(Radial Base Function) 기법을 적용하여 수율 저하의 원인이 되는 문제 장비나 문제 파라미터를 신속, 정확하게 파악할 수 있도록 해 줄 뿐만 아니라 공정 진행 중인 제품의 미래 수율을 예측할 수 있도록 지원하는 방법을 제안한다. 또한 위 기법들을 반도체 FAB공정을 대상으로 국내 모 반도체 회사에서 정보시스템으로 구현한 Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis ＆ Up Support) 시스템을 소개한다.

• 제어로봇시스템학회논문지
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• 제21권9호
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• pp.875-880
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• 2015

Traditional semiconductor process control has been performed through statistical process control techniques in a constant process-recipe conditions. However, the complexity of the interior of the etching apparatus plasma physics, quantitative modeling of process conditions due to the many difficult features constraints apply simple SISO control scheme. The introduction of the Advanced Process Control (APC) as a way to overcome the limits has been using the APC process control methodology run-to-run, wafer-to-wafer, or the yield of the semiconductor manufacturing process to the real-time process control, performance, it is possible to improve production. In addition, it is possible to establish a hierarchical structure of the process control made by the process control unit and associated algorithms and etching apparatus, the process unit, the overall process. In this study, the research focused on the methodology and monitoring improvements in performance needed to consider the process management of future developments in the semiconductor manufacturing process in accordance with the age of the APC analysis in real applications of the semiconductor manufacturing process and process fault diagnosis and control techniques in progress.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.44-44
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• 2009

Fault detection is necessary for yield enhancement and cost reduction in semiconductor manufacturing. Sensory data acquired from the semiconductor processing tool is too large to analyze for the purpose of fault detection and classification(FDC). We studied the techniques of fault detection using statistical method. Multiple regression analysis smoothly detected faults and can be easy made a model. For real-time and fast computing time, the huge data was analyzed by each step. We also considered interaction and critical factors in tool parameters and process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.236-250
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• 2016

Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.