• 한국컴퓨터정보학회논문지
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• 제12권6호
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• pp.139-146
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• 2007

컴퓨터시스템에서 메모리시스템은 계층적인 구조를 갖는다. 외부기억장치에 해당하는 디스크는 용량이 크고 가격이 저렴하지만 동작은 기계적인 특성에 기반을 두고 있어 주기억장치에 비하여 매우 느리고 디스크의 성능 향상도 매우 느리게 이루어지고 있지만 처리기는 반도체기술의 발전으로 속도향상이 매우 빠르게 이루어지고 있다. 따라서 저속의 디스크 입출력서브시스템은 컴퓨터시스템의 전체 성능에 병목(bottle neck)을 일으키고 있다. 컴퓨터시스템내의 디스크 입출력 서브시스템의 성능을 개선함으로 컴퓨터시스템의 전체 성능개선을 실현하는 연구가 이루어지고 있다. 본 논문에서는 처리기가 필요로 할 가능성이 높은 디스크블록을 버퍼캐시와 디스크 캐시에 효율적으로 유지하여 디스크블록 평균접근시간을 줄임으로 컴퓨터시스템의 성능을 향상시키는 개선된 알고리즘인 multi-level LRU 기법을 제안하였고 이를 버퍼캐시와 디스크 캐시를 가지는 시스템에 적용하였다. 시뮬레이션을 통하여 제안된 방안의 성능을 평가하였다.

• 대한전자공학회논문지TC
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• 제43권10호
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• pp.46-54
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• 2006

본 논문에서는 기존의 아날로그 트랜시버가 가지고 있는 단점을 극복하기 위한 디지털 트랜시버를 제안한다. 제안된 트랜시버는 불연속적인 협대역 채널들로 구성된 환경에서 사용된다고 가정하였다. 그리고 어느 정도의 보안성을 가지며 개인 대(對) 개인뿐만 아니라, 개인 대(對) 그룹, 그룹 대(對) 그룹의 음성 및 데이터 통신이 가능하여야 하며, 음성과 데이터를 동시에 전송할 경우 1 Mbps의 데이터 율을 가져야 한다고 가정하였다. 주파수 대역의 제한 때문에 FH-SS(Frequency Hopping-Spread Spectrum) 방식을, 구현의 복잡성 때문에 D8PSK(Differential 8 Phase Shift Keying) 방식을 채택하였다. 반송파와 심볼 타이밍 복원을 위해 IEEE 802.11 FHSS 프레임 구조를 바탕으로 새로운 프리앰블 구조를 제안하여 검출 확률을 높였다. 전산 모의 실험과 전력 계산을 통하여 제안된 시스템은 아날로그 워키토키와 같은 간단한 무선 통신에 사용될 수 있음을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.51-55
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• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1441-1444
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• 2008

We developed ultra-accelerated quantum chemical molecular dynamics and spectroscopic characterization simulators for development of PDP materials. By combination of these simulators, realistic structure of PDP materials is drawn on the computer. Furthermore, based on the structures, various properties such as cathode luminescence spectrum and secondary electron emission, is successfully evaluated. The strategy of "Experiment integrated Computational Chemistry" using developed simulators will presented that has the potential in being powerful tool for designing the PDP materials.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2000년도 춘계종합학술대회
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• pp.442-446
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• 2000

MOSFET는 속도의 증가, 전력 감소 그리고 집적도 증가를 위한 끊임없는 요구에 대응하여 최근 10년간 많은 변화를 겪었다. 그로 인한 스켈링이론이 부각되었고 풀 밴드 Monte Carlo 디바이스 시뮬레이터는 다른 형태의 n-channel MOSFET 구조에서 hot carrier에 대한 디바이스 스켈링의 효과를 연구하는데 사용되었다. 본 연구에서는 단일 Source/Drain 주입의 Conventional MOSFET와 저도핑 Drain(LDD) MOSFEI 그리고 MOSFET을 고도핑된 ground plane 위에 적충하여 만든 EPI MOSFET에 대하여 TCAD(Technology Compute. Aided Design)를 사용하여 스켈링 및 시뮬레이션하였다. 스켈링방법은 Constant-Voltage 스켈링을 사용하였고 시뮬레이션 결과로 스켈링에 대한 MOSFET의 특성과 임팩트 이온화, 전계를 비교 분석을 통해 TCAD의 실용성을 살펴보았고 스켈링을 이해하기 위한 물리적인 토대를 제시하였다.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 추계학술대회
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• pp.726-729
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• 2010

고밀도집적을 위하여 전기도금과 무전해도금법을 적용하여 구리기둥주석범프(CPTB)를 제작하고, 그 특성을 분석하였다. CPTB는 ${\sim}100{\mu}m$의 피치를 갖도록 KM-1250 건식감광필름(DFR)을 사용하여 먼저 구리 기둥범프(CPB)를 도금 전착시킨 다음, 구리의 산화억제를 위하여 그 위에 주석을 무전해 도금하였다. 열-압력에 따른 산화효과와 접합특성을 위하여 전기저항계수와 기계적 층밀림전단강도를 측정하였다. 전기저항계수는 산화두께의 증가에 따라서 증가하였고, 전단강도는 $330^{\circ}C$에서 500 N의 열-압력일 때 최고치를 나타냈다. 시뮬레이션 결과에 따르면, CPTB는 크기 감소의 결과를 나타냈으며, 그것은 구리의 산화에 의해 크게 영향을 받는 것으로 확인되었다.

• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.120-125
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• 2010

For the fabrication of PMOS and integrated semiconductor devices, B, $BF_2$ and dual elements with B and $BF_2$ can be implanted in silicon. 15 keV B ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{16}\;cm^{-2}$. 67 keV $BF_2$ ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{15}\;cm^{-2}$. For dual implantations, 67 keV $BF_2$ and 15keV B were carried out with two implantations with dose of $1.5{\times}10^{15}\;cm^{-2}$ instead of $3.0{\times}10^{15}\;cm^{-2}$, respectively. For the electrical activation, the implanted samples were annealed with rapid thermal annealing at $1,050^{\circ}C$ for 30 seconds. The implanted profiles were characterized by using secondary ion mass spectrometry in order to measure profiles. The implanted and annealed results show that concentration profiles for the ${BF_2}^+$ implant are shallower than those for a single $B^+$ and dual ($B^+$ and ${BF_2}^+$) implants in silicon. This effect was caused by the presence of fluorine which traps interstitial silicon and ${BF_2}^+$ implants have lower diffusion effect than a single and dual implantation cases. For the fabricated diodes, current-voltage (I-V) and capacitance-voltage (C-V) were also measured with HP curve tracer and C-V plotter. Electrical measurements showed that the dual implant had the best result in comparison with the other two cases for the turn on voltage characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.131-131
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• 2010

The power of semiconductor laser diodes has been limited primarily by the heating effects which occur at high optical intensities. The actual limiting event can take one of a number of forms such as. catastrophic optical damage or filamentation. A general approach to this problem is to design a heterostructure which creates a high powered output while maintaining low internal optical intensities. A graded index separate confinement heterostructure (GRIN-SCH) is one such structure that accomplishes the above task. Here, the active region is sandwiched between graded index layers where the index of refraction increases nearer to the active layer. This structure has been shown to yield a high efficiency due to the confinement of both the optical power and carriers, thereby reducing the optical intensity required to achieve higher powers. The optical confinement also reinforces the optical beam quality against high power effects. Quantum dots have long been a desirable option for laser diodes due to the enhanced optical properties associated with the zeroth dimensionality. In our work, we use PICS3D software created by Crosslight Software Inc. to simulate the performance of In0.67A10.33As/A10.2Ga0.8AsquantumdotsusedwithaGRIN-SCH. The simulation tools are used to optimize the GRIN-SCH structure for high efficiency and optical beam quality.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.47-52
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• 2013

Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.