• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.808-816
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• 2016

As the number of CPU/GPU cores and IPs in SOC increases and applications require explosive memory bandwidth, simultaneously achieving good throughput and fairness in the memory system among interfering applications is very challenging. Recent works proposed priority-based thread scheduling and channel partitioning to improve throughput and fairness. However, combining these different approaches leads to performance and fairness degradation. In this paper, we analyze the problems incurred when combining priority-based scheduling and channel partitioning and propose dynamic priority thread scheduling and adaptive channel partitioning method. In addition, we propose dynamic address mapping to further optimize the proposed scheme. Combining proposed methods could enhance weighted speedup and fairness for memory intensive applications by 4.2% and 10.2% over TCM or by 19.7% and 19.9% over FR-FCFS on average whereas the proposed scheme requires space less than TCM by 8%.

• IE interfaces
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• v.17 no.spc
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• pp.131-140
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• 2004

The purpose of this paper is to develop and show the efficiency of the URL(Unload Request Logic) and LRL(Load Request Logic) of the dispatcher in the Fab(Fabrication) Manufacturing Execution System. These logics are the core procedures which control the material(wafer and glass substrate) flow efficiently in the semiconductor and LCD fab considering inter-bay as well as intra-bay material flow. We use the present and future status information of the system by look-ahead and the information about the future transportation schedule of Automated Guided Vehicles. The simulation results show that the URL and LRL presented in this paper reduce the average lead time, average and maximum WIP level, and the average available AGV waiting time.

• Journal of Korean Institute of Industrial Engineers
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• v.34 no.3
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• pp.296-307
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• 2008

A semiconductor production system has sophisticated manufacturing operations and needs high capital investment for its expensive equipment, which warrants efficient real-time flow control for wafers. In the bay, we consider material handling equipment that can handle multiple carriers of wafers. The dispatching logic first determines the transportation time of each carrier to its destination by each unit of transportation equipment and uses this information to determine the destination machine and target carrier. When there is no available buffer space at the machine tool, the logic allows carriers to stay at the buffer of a machine tool and determine the delay time, which is used to determine the destination of carriers in URL. A simulation study shows this dispatching logic performs better than the procedure currently in use to reduce the mean flow time and average WIP of wafers and increase efficiency of material handling equipment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.9
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• pp.1330-1335
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• 2012

This paper proposes an automatic measurement sampling method for the semiconductor manufacturing process. The method recommends sampling rates using information of process capability indexes and production scheduling plan within the restricted metrology capacity. In addition, it automatically controls the measurement WIP (Work In Process) using measurement priority values to minimize the measurement risks and optimize the measurement capacity. The proposed sampling method minimizes measurement controls in the semiconductor manufacturing process and improves the fabrication productivity via reducing measurement TAT (Turn Around Time), while guaranteeing the level of process quality.

• Journal of the Korea Society for Simulation
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• v.8 no.3
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.

• Journal of the Korea Society of Computer and Information
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• v.19 no.6
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• pp.101-108
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• 2014

The parallel machine scheduling is to schedule each job to exactly one parallel machine so that the total completion time is minimized. It is used in various manufacturing system areas such as steel industries, semiconductor manufacturing and plastic industries. Each job has a setup phase and a processing phase. A removal phase is needed in some application areas. A processing phase is performed by a parallel machine alone while a setup phase and a removal phase are performed by both a server and a parallel machine simultaneously. Most of previous researches used a single server and considered only a setup phase and a processing phase. If a single server is used for scheduling, the bottleneck in the server increases the total completion time. Even though the number of parallel machines is increased, the total completion time is not reduced significantly. In this paper, we have proposed an efficient algorithm for the parallel machine scheduling using multiple servers and considering setup, processing and removal phases. We also have investigated experimentally how the number of servers and the number of parallel machines affect the total completion time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.107-114
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• 2017

In beacon-enabled mode, beacon collision is a significant problem for the scalability of cluster-tree wireless sensor networks. In this paper, multi-channel time division scheduling (MCTS) is proposed to prevent beacon collisions and provide scalability. A coordinator broadcasts a beacon frame, including information on allocated channels and time-slots, and a new node determines its own channel and time-slot. The performance of the proposed method is evaluated by comparing the proposed approach with a typical ZigBee. MCTS prevents beacon collisions in cluster-tree wireless sensor networks. It enables large-scale wireless sensor networks based on a cluster tree to be scalable and effectively constructed.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.43-49
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• 2017

In this paper, we propose the scheduling scheme of IEEE802.15.4e TSCH which is not specified in standard specification. The proposed scheme schedules the link by cooperating among the devices. A new device scans EBs(Enhanced Beacons) from network. An advertiser device broadcasts an enhanced beacon frame including links information on allocated channel offset and time-slots, and a new device can determine its own channel offset and time-slot. It's performance on maximum throughput and minimum delay is evaluated by comparing the proposed approach with a typical single channel IEEE802.15.4.

• Journal of the Korea Society for Simulation
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• v.24 no.3
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• pp.17-26
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• 2015

A cluster tool used in many kinds of semiconductor processes for improving the performance and the quality of wafers has a simple configuration, but its schedule is not easy because of its parallel processing module, a lack of intermediate buffers, and time constraints. While there have been many studies on its schedule, most of them have focused on full cycles in which identical work cycles are repeated under constant task times. In this research, we suggest strategies of start-up transient scheduling which satisfies time constraints and converges into a desirable steady schedule for full work cycle. The proposed schedules are expected robust under the stationary stochastic task times. Finally, we show that the strategies make schedules enters the desirable steady schedule and robust using the simulation.