• Journal of the Korean Vacuum Society
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• v.18 no.5
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• pp.372-376
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• 2009

In the modern semiconductor industry, lithography process is used to construct specific patterns. However, due to the decreasing of line width, these days, more and more researchers are interested in PMMA(Poly Methyl Methacrylate) lithography by using e-beam instead of the prior method, PR(Photoresist) lithography by using UV(Ultra-Violet). Additionally, the patterns constructed by lithography are collapsed during the process of cleansing remnants and the resistance against the breakdown of the patterns is known to be proportional to the elastic modulus of pattern-constructing materials. In this research, we measured the change of hardness and elastic modulus of PMMA film surface according to the change of time spent to soft-bake the PMMA film. During the measurement, we controlled the tip pressure from $25{\mu}N$ to $8,500{\mu}N$ having intervals that are $134.52{\mu}N$. For these measurements, we used the Triboindenter from Hysitron to gauge the hardness and elastic modulus and the tip we used was Berkovich diamond Tip.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.20 no.4
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• pp.178-184
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• 2010

The $12CaO{\cdot}7Al_2O_3$(C12A7) powders were successfully synthesized using combustion method with microwave-assistant and C12A7:H were fabricated by post-annealed process in Ar/H atmosphere. X-ray diffraction patterns and TGDSC were used for investigating to the precursors of crystalline and reaction depending on temperature. C12A7:H that was treated post-annealed process were investigated TG-MS and Hall-measurement for confirming H ions doping and checking electrical resistivity of C12A7:H. H ion substituted to $O^{2-}$ ions in the C12A7 cages were confirmed at $289.5^{\circ}C$ by TG-MS and C12A7:H calcined at $1000^{\circ}C$ in Ar/H=8:2 atmosphere for 8~10 h has low electrical resistivity about $10^2{\Omega}{\cdot}cm$ at room temperature.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.229-229
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• 2010

With the scaling down of ultra large integrated circuits (ULSI) to the sub-50 nm technology node, the need for an ultra-thin, continuous and conformal diffusion barrier and Cu seed layer is increasing. However, diffusion barrier and Cu seed layer formation with a physical vapor deposition (PVD) method has become difficult as the technology node is reduced to 30 nm and beyond. Recent work on self-forming barrier processes using PVD Cu alloys have attracted great attention due to the capability of conformal ultra-thin barrier formation using a simple technique. However, as in the case of the conventional barrier and Cu seed layer, PVD of the Cu alloy seed layer will eventually encounter the difficulty in conformal deposition in narrow line trenches and via holes. Atomic layer deposition (ALD) has been known for its good step coverage and precise thickness control, and is a candidate technique for the formation of a thin conformal barrier layer and Cu seed layer. Conformal Cu-Mn seed layers were deposited by plasma enhanced atomic layer deposition (PEALD) at low temperature ($120^{\circ}C$), and the Mn content in the Cu-Mn alloys were controlled form 0 to approximately 10 atomic percent with various Mn precursor feeding times. Resistivity of the Cu-Mn alloy films decreased by annealing due to out-diffusion of Mn atoms. Out-diffused Mn atoms were segregated to the surface of the film and interface between a Cu-Mn alloy and $SiO_2$, resulting in self-formed $MnO_x$ and $MnSi_xO_y$, respectively. No inter-diffusion was observed between Cu and $SiO_2$ after annealing at $500^{\circ}C$ for 12 h, indicating an excellent diffusion barrier property of the $MnSi_xO_y$. The adhesion between Cu and $SiO_2$ was enhanced by the formation of $MnSi_xO_y$. Continuous and conductive Cu-Mn seed layers were deposited with PEALD into 32 nm $SiO_2$ trench, enabling a low temperature process, and the trench was perfectly filled using electrochemical plating (ECD) under conventional conditions. Thus, it is the resultant self-forming barrier process with PEALD Cu-Mn alloy film as a seed layer for plating Cu that has further potential to meet the requirement of the smaller than 30 nm node.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.221-221
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• 2013

Vertical LED (VLED) has been recognized as a way to obtain the high-power LED due to their advantages [1]. However, approximately 4% of the light generated from the active region is extracted, if the light extraction from side walls and back side is neglected because of Fresnel reflection (FR) and total internal reflection (TIR) [2,3]. In this study, the optical simulation of the VLED with the various microstructures was performed. Among them, the microlens having the diameter of 3 ${\mu}m$ and the height of 1.5 ${\mu}m$ shown the best result was chosen, and then, optimized microlens was formed on a GaN template using conventional semiconductor process. Various microstructures were proposed to improve the light extraction efficiency (LEE) of the VLED for the simulation. The LEE was simulated using LightTools based on a Monte Carlo ray tracing. The microstructures with hemisphere, cone, truncated and cylinder pattern having diameter of 3 ${\mu}m$ were employed on the top layer of the VLED respectively. The improvement of the LEE by using the microstructure is 87% for the hemisphere, 77% for the cone, 53% for the truncated, 21% for the cylinder, compared with the LEE of the flat surface at the reflectance of 85%. The LEE was increased by 88% at the height of 1.5 ${\mu}m$, compared with the LEE of the flat surface. We found that the microlens on the top layer is the most suitable for increasing the LEE. In order to apply the proposed microlens on n-GaN surface, we fabricated microlens on a GaN template. A photoresist array having hexagonal-closed packed microlens was fabricated on the GaN template. Then, optimization of etching the GaN template was performed using a dry etching process with ICP-RIE. The dry etching carried out using a gas mixture of Cl2 and Ar, each having a flow rate of 16 sccm and 10 sccm, respectively with RF power of 50 W, ICP power of 900 W and chamber pressure of 2 mTorr was the optimum etching condition as shown in Fig. 2(a).

• Korean Journal of Optics and Photonics
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• v.29 no.1
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• pp.19-27
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• 2018

A change in object distance would generally change the magnification of an optical system. In this paper, we have proposed and designed a double-Gauss optical system with a fixed magnification and image surface regardless of any change in object distance, according to moving the lens groups a little bit to the front and rear of the stop, independently parallel to the direction of the optical axis. By maintaining a constant size of image formation in spite of various object-distance changes in a projection system such as a head-up display (HUD) or head-mounted display (HMD), we can prevent the field of view from changing while focusing in an HUD or HMD. Also, to check precisely the state of the wiring that connects semiconductor chips and IC circuit boards, we can keep the magnification of the optical system constant, even when the object distance changes due to vertical movement along the optical axis of a testing device. Additionally, if we use this double-Gauss optical system as a vision system in the testing process of lots of electronic boards in a manufacturing system, since we can systematically eliminate additional image processing for visual enhancement of image quality, we can dramatically reduce the testing time for a fast test process. Also, the Gaussian bracket method was used to find the moving distance of each group, to achieve the desired specifications and fix magnification and image surface simultaneously. After the initial design, the optimization of the optical system was performed using the Synopsys optical design software.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.3
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• pp.29-34
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• 2019

Silicon carbide is considered to be a potentially useful material for high-temperature electronic devices, as its large energy band gap and the p-type and/or n-type conduction can be controlled by impurity doping. Particularly, electric conductivity of porous n-type SiC semiconductors fabricated from ${\beta}-SiC$ powder at $2000^{\circ}C$ in $N_2$ atmosphere was comparable to or even larger than the reported values of SiC single crystals in the temperature region of $800^{\circ}C$ to $1000^{\circ}C$, while thermal conductivity was kept as low as 1/10 to 1/30 of that for a dense SiC ceramics. In this work, for the purpose of decreasing sintering temperature, it was attempted to fabricate porous reaction-sintered bodies at low temperatures ($1400-1600^{\circ}C$) by thermal decomposition of polycarbosilane (PCS) impregnated in n-type ${\beta}-SiC$ powder. The repetition of the impregnation and sintering process ($N_2$ atmosphere, $1600^{\circ}C$, 3h) resulted in only a slight increase in the relative density but in a great improvement in the Seebeck coefficient and electrical conductivity. However the power factor which reflects the thermoelectric conversion efficiency of the present work is 1 to 2 orders of magnitude lower than that of the porous SiC semiconductors fabricated by conventional sintering at high temperature, it can be stated that thermoelectric properties of SiC semiconductors fabricated by the present reaction-sintering process could be further improved by precise control of microstructure and carrier density.

• Analytical Science and Technology
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• v.35 no.5
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• pp.205-211
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• 2022

Deuterium (D) is an isotope with one more neutron number than hydrogen (H). Heavy elements rarely change their chemical properties with little effect even if the number of neutrons increases, but low-mass elements change their vibration energy, diffusion rate, and reaction rate because the effect cannot be ignored, which is called an isotope effect. Recently, in the semiconductor and display industries, there is a trend to replace hydrogen gas (H₂) with deuterium gas (D₂) in order to improve process stability and product quality by using the isotope effect. In addition, as the demand for D₂ in industries increases, domestic gas producers are making efforts to produce and supply D₂ on their own. In the case of high purity D₂, most of them are produced by electrolysis of heavy water (D₂O), and among D₂, hydrogen deuteride (HD) molecules are present as isotope impurities. Therefore, in order to maximize the isotope effect of hydrogen in the electronic industry, HD, which is an isotope impurity of D₂ used in the process, should be small amount. To this end, purity analysis of D₂ for industrial processing is essential. In this study, HD quantitative analysis of D₂ for high purity D₂ purity analysis was established and hydrogen isotope RM (Reference material) was developed. Since hydrogen isotopes are difficult to analyze with general gas analysis instrument, they were analyzed using a high-precision mass spectrometer (Gas/MS, Finnigan MAT271). High purity HD gas was injected into Gas/MS, sensitivity was determined by a signal according to pressure, and HD concentrations in two bottles of D₂ were quantified using the corresponding sensitivity. The amount fraction of HD in each D₂ was (4518 ± 275) μmol/mol, (2282 ± 144) μmol/mol. D₂, which quantifies HD amount using the developed quantitative analysis method, will be manufactured with hydrogen isotope RM and distributed for quality management and maintenance of electronic industries and gas producers in the future.