• Proceedings of the Korean Vacuum Society Conference
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• 1996.06a
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• pp.96-96
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• 1996

• Proceedings of the Materials Research Society of Korea Conference
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• 1997.05a
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• pp.27-27
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• 1997

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.275-286
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• 2015

In this paper, we propose a practical method for setting up a daily production plan which can operate semiconductor fabrication factories more stably and linearly by determining work in process (WIP) targets and movement targets. We first adjust cycle times of the operations to satisfy the monthly production plan. Second, work in process (WIP) targets are determined to control the production progress of operations: earliness and tardiness. Third, movement targets are determined to reduce cumulated differences between WIP targets and actual WIPs. Finally, the determined movement targets are modified through a simulation model which considers capacities of the equipments and allocations of the WIPs in the fab. The proposed daily production planning method can be easily adapted to the memory semiconductor fabs because the method is very simple and has straightforward logics. Although the proposed method is simple and straightforward, the power of the method is very strong. Results from the shop floor in past few periods showed that the proposed methodology gives a good performance with respect to the productivity, workload balance, and machine utilization. We can expect that the proposed daily production planning method will be used as a useful tool for operating semiconductor fabrication factories more efficiently and effectively.

• Journal of Korean Society for Quality Management
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• v.47 no.4
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• pp.725-737
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• 2019

Purpose: We used a data analysis method to improve semiconductor manufacturing yield. We defined and optimized important factors and applied our findings to a real-world process. The semiconductor industry is very cost-competitive; our findings are useful. Methods: We collected data on 15 independent variables and one dependent variable (yield); we removed outliers and missing values. Using SPSS Modeler ver. 18.0, we analyzed the data both continuously and discretely and identified common factors. Results: We optimized two independent variables in terms of process conditions; yield improved. We used DS Leak software to model netting and Contact CD software to model meshes. DS Leak shows smaller the better characterisrics and Contact CD shows normal the best characteristics Conclusion: Various efforts have been made to improve semiconductor manufacturing yields, and many studies have created models or analyzed various characteristics. We not only defined important factors but also showed how to control processing to improve semiconductor yield.

• Journal of the Korean Vacuum Society
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• v.13 no.2
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• pp.59-64
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• 2004

A study on the semiconductor laser-based atomic absorption spectroscopy was performed for monitoring physical vapor deposition process. Gadolinium metal was vaporized with a high evaporation rate by electron beam heating. Real-time atomic absorption spectra were measured by using tunable semiconductor laser beam at 770-794 nm (center wavelength of 780 nm) and its second harmonic at 388-396 nm. Atomic densities of metal vapor can be calculated from the absorption spectra measured. We plot the atomic densities as a function of the electron beam power and compare with the evaporation rates measured by quartz crystal monitor. We demonstrate that the semiconductor laser-based spectroscopic system developed in this study can be applied to monitor the physical vapor deposition process for other metals such as titanium.

• Analytical Science and Technology
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• v.5 no.4
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• pp.455-464
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• 1992

Using FT-IR, we determined the depth of silylated layers produced from various gas-phase-silylation conditions was proposed by using Fourier Transform Infrared (FT-IR) spectroscopic analysis. The depth of silylated layer was determined from absorbance measurments of the significant peaks (Si-O-ph, Si-C, Si-H) of FT-IR spectra with background spectrum subtraction method. And the results were compared with thickness measurments of SEM. The results were well agree with SEM. It found to be well suited for determining silylation process window.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.45-48
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• 2002

This paper discusses the surface roughness of negative chemically amplified resists, SAL601 exposed by I-beam direct writing. system. Surface roughness, as measured by atomic force microscopy, have been simulated and compared to experimental results. Molecular-scale simulator predicts the roughness dependence on material properties and process conditions. A chemical amplification is made to occur in the resists during PEB process. Monte-Carlo and exposure simulations are used as the same program as before. However, molecular-scale PEB simulation has been remodeled using a two-dimensional molecular lattice representation of the polymer matrix. Changes in surface roughness are shown to correlate with the dose of exposure and tile baking time of PEB process. The result of simulation has a similar tendency with that of experiment.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.144-149
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• 2022

A cryogenic Mixed Refrigerant Joule-Thomson refrigeration cycle was designed to be applied to the semiconductor etching process with non-flammable constituents. 3-stage cascade refrigerator, single mixed refrigerant Joule-Thomson refrigerator, and 2-stage cascade type mixed refrigerant Joule-Thomson refrigerator are analyzed to figure out the coefficient of performance. Non-flammable mixture of argon(Ar), tetrafluoromethane(R14), trifluoromethane (R23) and octafluoropropane(R218) were utilized to analyze the refrigeration cycle efficiency. The designed refrigeration cycle was adapted to cool down the coolant of HFE7200(Ethoxy-nonafluorobutane, C₄F₉OC₂H₅) with certain constraints. Maximum coefficient of performance of the refrigeration system is obtained as 0.289 for the cooling temperature lower than -100℃. The detailed result of the coefficient of performance according to the mixture composition is discussed in this study.

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2008.05a
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• pp.23-29
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• 2008

- High Density Plasma Source-CCP-Dual/Triple, RF Frequency Control - Radical/Flux Analysis - Low Pressure Process - Chamber Design (Process gap/Wall gap) - Chamber Temp. Control. - ESC Dielectric Materials - Uniform Gas Injection