• 한국결정성장학회지
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• 제32권2호
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• pp.55-60
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• 2022

본 연구에서는 SiC 단결정의 TSSG 공정중 결정 품질을 저하시키지 않으면서도 의도하지 않은 질소 도핑(N-UID)을 쉽게 제어하기 위해 지금까지 Co 또는 Sc 전이금속을 첨가한 신규 용융조성을 제안한다. Co 또는 Sc의 특성을 파악하기 위해 Ar 분위기에서 1900℃ 온도에서 약 2시간 동안 열처리 실험을 수행했다. 용융조성은 Si-Ti 10 at% 또는 Si-Cr 30 at%를 비롯하여, 탄소 용해도에 효과적이라고 알려진 Co 또는 Sc을 각각 3 at% 첨가하였다. 열처리 후 도가니 단면을 가공하여 도가니-용융물 계면에서 발생한 Si-C 반응층을 관찰하고, 탄소황분석을 통해 조성에 따른 탄소 용해도를 간접적으로 분석하였다. 그 결과, Si-Sc 기반 용융조성이 TSSG 공정에 적합한 특성을 갖는 Si-C반응층을 형성하고 있었다. 또한 탄소황분석 결과에서도 Cr 다음으로 높은 탄소량이 갖는 것으로 분석되었다. Sc는 Cr에 비해 질소와의 반응성이 낮은 이점을 가지므로 TSSG 공정에 Si-Sc 용융조성을 적용하면, 본 연구에서 의도한 대로 SiC 단결정 성장속도와 질소 UID를 모두 제어할 수 있는 것으로 고려된다.

• Current Photovoltaic Research
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• 제7권4호
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• pp.125-129
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• 2019

Recently, carrier-selective contact solar cells have attracted much interests because of its high efficiency with low recombination current density. In this study, we investigated the effect of phosphorus doped amorphous silicon layer's characteristics on the passivation properties of tunnel oxide passivated carrier-selective contact solar cells. We fabricated symmetric structure sample with poly-Si/SiOx/c-Si by deposition of phosphorus doped amorphous silicon layer on the silicon oxide with subsequent annealing and hydrogenation process. We varied deposition temperature, deposition thickness, and annealing conditions, and blistering, lifetime and passivation quality was evaluated. The result showed that blistering can be controlled by deposition temperature, and passivation quality can be improved by controlling annealing conditions. Finally, we achieved blistering-free electron carrier-selective contact with 730mV of i-Voc, and cell-like structure consisted of front boron emitter and rear passivated contact showed 682mV i-Voc.

• 디지털융복합연구
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• 제15권9호
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• pp.211-221
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• 2017

반도체 산업은 임베디드 소프트웨어를 통해 운영 통제되는 자동화설비를 통해 첨단상품을 생산한다. 반도체를 생산하는 로봇과 각종 설비의 임베디드 소프트웨어 유지보수는 제품의 품질과 신뢰성 제고를 위한 필수적인 과정으로 반도체 장비의 라이프 사이클을 고려할 때 상당히 높은 비중을 차지하는 활동영역이다. 그러나 이 분야에 대한 학술적 관심사는 그리 높지 않는데, 본 연구에서는 반도체 웨이퍼 생산장비를 구동하는 소프트웨어 관련 문제로 보고된 사건을 대상으로 502개의 데이터를 무작위 추출방식으로 수집하여 임베디드 소프트웨어의 유지보수 노력에 영향을 미치는 요인들을 분석해 보았다. 결론으로 실무적인 시사점도 제시하였다.

• 한국산업융합학회 논문집
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• 제7권3호
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• pp.259-263
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• 2004

In the manufacture progress of LCD or semiconductor, there are used many kinds of gas like erosion gas, dilution gas, toxic gas as a progress which used these gas there are required high puritize to increase accumulation rate of semiconductor or LCD materials work progress of semiconductor or LCD it demand many things like the material which could minimize metallic dust that could be occured by reaction between gas and transfer pipe laying material, illumination of the surface, emition of the gas, metal liquation, welding etc also demand quality geting stricted. Material-Low-sulfur-contend (0.007-0010), vacuum-arc-remelt(VAR), seamless, high-purity tubing material is recommend for enhance welding lower surface defect density All wetted stainless steel surface must be 316LSS elecrto polishinged with ${\leq}0.254{\mu}m$($10.0{\mu}in$) Ra average surface finish, $Cr/Fe{\geq}1.1$ and $Cr_2O_3$ thickness ${\geq}25{\AA}$ From the AES analytical the oxide layer thickness (23.5~36 angstroms silicon dioxide equivalent) and chromum to iron ratios is similar to those generally found on electropolished stainless steel., molybdenum and silicon contaminants ; elements characteristic of stainless steel (iron, nickel and chromium); and oxygen were found on the surface Phosphorus and nitrogen are common contaminants from the electropolish and passivation steps.

• 한국결정성장학회지
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• 제28권4호
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• pp.159-165
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• 2018

최근 전세계적으로 환경오염 및 에너지 고갈에 대한 대책 마련의 일환으로 에너지 재생 및 절약 소자인 고효율 친환경 전력반도체로서 GaN 전력소자에 대한 관심이 고조되어가고 있다. 이를 위해서, GaN 단결정 기판의 사용이 절실히 요구되는 바, Yole사 보고서(2013)와 국내 외 GaN 관련 산학연의 최신 발표(2017)를 바탕으로 최근 GaN 단결정 산업동향을 리뷰하였다. GaN 단결정 기판에 대한 연구개발은 저결함, 대구경을 목표로 지속적으로 진행되고 있으나, 아직 시장형성이 활성화되고 있지 못하다.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.101.1-101.1
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• 2016

Van der Waals (vdW) heterostructures built from two-dimensional layered materials provide an unprecedented opportunity in designing new material systems because the lack of dangling bonds on the vdW surfaces enables the creation of high-quality heterointerfaces without the constraint of atomically precise commensurability. In particular, the ability to build artificial heterostructures, combined with the recent advent of transition metal dichalcogenides, allows the fabrication of unique semiconductor heterostructures in an ultimate thickness limit for fundamental studies as well as novel device applications. In this talk, we will present the characterization of the electronic and optoelectronic properties of atomically thin p-n junctions consisting of vertically stacked WSe2 and MoS2 monolayers. We observed gate-tunable diode-like current rectification and a photovoltaic response across the p-n interface. Unlike conventional bulk p-n junctions, the tunneling-assisted interlayer recombination of the majority carriers is responsible for the tenability of the charge transport and the photovoltaic response. Furthermore, we will discuss the enhanced optoelectronic characteristics in graphene-sandwiched vdW p-n junctions.

• 반도체디스플레이기술학회지
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• 제10권3호
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• pp.61-65
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• 2011

The capabilities of finite elements codes allow now accurate simulations of blanking processes when appropriate materials modelling are used. Over the last decade, numerous numerical studies have focused on the influence of process parameters such as punch-die clearance, tools geometry and friction on blanking force and blank profile. In this study, three dimensional finite element analysis is carried out to design a lead frame blanking die using LS-Dyna3D package. After design of the blanking die, an experiment is also carried out to investigate the characteristics of blanking for nickel alloy Alloy42, a kind of IC lead frame material. In this paper, it has been researched the investigation to examine the influence of process parameters such as clearance and air cylinder pressure on the accuracy of sheared plane. Through the experiment results, it is shown that the quality of sheared plane is less affected by clearance and air cylinder pressure.

• 반도체디스플레이기술학회지
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• 제7권1호
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• pp.35-40
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• 2008

In OLED vacuum evaporation process, the essential requirements include good uniformity of the film thickness over a glass substrate. And, it is commercially significant to improve the consuming efficiency of material of the evaporant which is deposited on the substrate because of high price of organic materials. In this paper, to achieve the better thickness uniformity and the better organic material consuming rate, a process optimization algorithm was developed by understanding vacuum evaporation process parameters that affect the material consuming efficiency and the uniformity of film thickness. Based on the method developed in this study, the vacuum evaporation process of OLED was successfully controlled. The developed method allowed the manufacture of high quality OLED displays with cheaper fabrication cost.

• 반도체디스플레이기술학회지
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• 제15권3호
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• pp.6-11
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• 2016

Silicon wafer is one of main materials in solar cell. Micro-cracks in silicon wafer are one of reasons to decrease efficiency of energy transformation. They couldn't be observed by human eye. Also, their shape is not only various but also complicated. Accordingly, their shape classification is absolutely needed for manufacturing process quality and its feedback. The performance of typical classification techniques which is principal component analysis(PCA), neural network, fusion model to integrate PCA with neural network, and support vector machine(SVM), are evaluated using pattern features of micro-cracks. As a result, it has been confirmed that the SVM gives good results in micro-crack classification.