• Title/Summary/Keyword: self bias voltage

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Fabrication of Mo-tip Field Emitter Array and Diamond-like Carbon Coating Effects (몰리브덴 팁 전계 방출 소자의 제조 및 다이아몬드 상 카본의 코팅효과)

  • Ju, Byeong-Kwon;Jung, Jae-Hoon;Kim, Hoon;Lee, San-Jo;Lee, Yun-Hi;Tchah, Kyun-Hyon;Oh, Myung-Hwan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.7
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    • pp.508-516
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    • 1998
  • Mo-tip field emitter arrays(FEAs) were fabricated by conventional Spindt process and their life time characteristics and failure mode were evaluated. The fabricated Mo-tip FEA could generate at least $0.35\{mu} A/tip$ emission current for about 320 persistently under a constant gate bias of 140 V and was finally destroyed through self-healing mode. Thin diamond-like carbon films were coated on the M-tip by plasma-enhanced CVD and the dependence of emission properties upon the DLC thickness was investigated. By DLC coating, the turn-on voltage and emission current were appeared to be improved whereas the current fluctuation was increased in the DLC thickness range of $0~1,000\{AA}$.

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Manufacturing and characterization of ECR-PECVD system (ECR-PECVD 장치의 제작과 특성)

  • 손영호;정우철;정재인;박노길;황도원;김인수;배인호
    • Journal of the Korean Vacuum Society
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    • v.9 no.1
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    • pp.7-15
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    • 2000
  • An ECR-PECVD system with the characteristics of high ionization rat다 ability of plasma processing in a wide pressure range and deposition at low temperature was manufactured and characterized for the deposition of thin films. The system consists of a vacuum chamber, sample stage, vacuum gauge, vacuum pump, gas injection part, vacuum sealing valve, ECR source and a control part. The control of system is carried out by the microprocessor and the ROM program. We have investigated the vacuum characteristics of ECR-PECVD system, and also have diagnosed the characteristics of ECR microwave plasma by using the Langmuir probe. From the data of system and plasma characterization, we could confirmed the stability of pressure in the vacuum chamber according to the variation of gas flow rate and the effect of ion bombardment by the negative DC self bias voltage. The plasma density was increased with the increase of gas flow rate and ECR power. On the other hand, it was decreased with the increase of horizontal radius and distance between ECR source and probe. The calculated plasma densities were in the range of 49.7\times10^{11}\sim3.7\times10^{12}\textrm{cm}^{-3}$. It is also expected that we can estimate the thickness uniformity of film fabricated by the ECR-PECVD system from the distribution of the plasma density.

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Photoelectrochemical Properties of a Vertically Aligned Zinc Oxide Nanorod Photoelectrode (수직으로 정렬된 산화아연 나노막대 광전극의 광전기화학적 특성)

  • Park, Jong-Hyun;Kim, Hyojin
    • Journal of the Korean institute of surface engineering
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    • v.51 no.4
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    • pp.237-242
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    • 2018
  • We report on the fabrication and photoelectrochemical (PEC) properties of a ZnO nanorod array structure as an efficient photoelectrode for hydrogen production from sunlight-driven water splitting. Vertically aligned ZnO nanorods were grown on an indium-tin-oxide-coated glass substrate via seed-mediated hydrothermal synthesis method with the use of a ZnO nanoparticle seed layer, which was formed by thermally oxidizing a sputtered Zn metal thin film. The structural and morphological properties of the synthesized ZnO nanorods were examined using X-ray diffraction and scanning electron microscopy, as well as Raman scattering. The PEC properties of the fabricated ZnO nanorod photoelectrode were evaluated by photocurrent conversion efficiency measurements under white light illumination. From the observed PEC current density versus voltage (J-V) behavior, the vertically aligned ZnO nanorod photoelectrode was found to exhibit a negligible dark current and high photocurrent density, e.g., $0.65mA/cm^2$ at 0.8 V vs Ag/AgCl in a 1 mM $Na_2SO_4$ electrolyte. In particular, a significant PEC performance was observed even at an applied bias of 0 V vs Ag/AgCl, which made the device self-powered.

Design of X-Band SOM for Doppler Radar (도플러 레이더를 위한 X-Band SOM 설계)

  • Jeong, Sun-Hwa;Hwang, Hee-Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.12
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    • pp.1167-1172
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    • 2013
  • This paper presents a X-band doppler radar with high conversion gain using a self-oscillating-mixer(SOM) that oscillation and frequency mixing is realized at the same time. To improve phase noise of the SOM oscillator, a ${\lambda}/2$ slotted square patch resonator(SSPR) was proposed, which shows high Q-factor of 175.4 and the 50 % reduced circuit area compared to the conventional resonator. To implement the low power system, low biasing voltage of 1.7 V was supplied. To enhance the conversion gain of the SOM, bias circuit is configured near the pinch-off region of transistor, and the conversion gain was optimized. The output power of the proposed SOM was -3.16 dBm at 10.65 GHz. A high conversion gain of 9.48 dB was obtained whereas DC Power consumption is relatively low about 7.65 mW. The phase noise is -90.91 dBc/Hz at 100 kHz offset. The figure-of-merit(FOM) of the proposed SOM was measured as -181.8 dBc/Hz, which is supplier to other SOMs by more than about 7 dB.

The Design of Low Noise Amplifier for Overall IMT-2000 Band Repeater (IMT-2000 중계기용 전대역 저잡음 증폭기 설계)

  • 유영길
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.39 no.4
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    • pp.409-412
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    • 2002
  • The LNA(Low Noise Amplifier) is designed for use in low cost commercial application covered fully IMT-2000 band(1920~2170MHz, BW=250MHz). It is optimized source inductance for source lead and designed to equivalent etched line. The LNA uses a high pass impedance matching network for noise match and simple structure. The bias circuit designs have been made self-biased with a negative voltage applied to gate. The power supply voltage is 8V, total current is 180mA. The LNA is biased at a Vgs of -0.4, Vds of 4V for first stage and Vds of 5V for second stage. The LNA is designed competitively for commercial product specification. The measured gain and noise figure of the completed amplifier was 20dB and 1dB, respectively. Also, input VSWR, P1dB and gain flatness was measured of 1.14 ~ l.3dB, 22.4dBm and $\pm$0.45dB, respectively. The designed LNA can be used for commercial product.

A Study on the Characterisitics of Reactive Ion Etching (Cylindrical Magnetron을 사용한 실리콘의 반응성 이온 건식식각의 특성에 관한 연구)

  • Yeom, Geun-Yeong
    • Korean Journal of Materials Research
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    • v.3 no.4
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    • pp.327-335
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    • 1993
  • Using a RF cylindrical magnetron operated with two electromagnets having a Helmholz configuration, RF magnetron plasma properties and characteristics of reactive ion ething of Si were investigated as a function of applied magnetic field strengths using 3mTorr $CF_4/H_2$ and $CHF_3$. Also, I-V characteristics of Schottky diodes, which were made of silicons etched under different applied magnetic field strengths and gas environments, were measured to investigate the degree of radiation damage during the reactive ion etching. As the magnetic field strent;th increased, ion densities and radical densities of the plasmas were increased linearly, however, the dc self-bias voltages induced on the powered electrode, where the specimen are located, were decreased exponentially. Maximum etch rates, which were 5 times faster than that etched without applied magnetic filed, were obtained using near lOOGauss, and, under these conditions, little or no radiation damages on the etched silicons were found.

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Metal Gate Electrode in SiC MOSFET (SiC MOSFET 소자에서 금속 게이트 전극의 이용)

  • Bahng, W.;Song, G.H.;Kim, N.K.;Kim, S.C.;Seo, K.S.;Kim, H.W.;Kim, E.D.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.358-361
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    • 2002
  • Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

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A Low Jitter Delay-Locked Loop for Local Clock Skew Compensation (로컬 클록 스큐 보상을 위한 낮은 지터 성능의 지연 고정 루프)

  • Jung, Chae-Young;Lee, Won-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.2
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    • pp.309-316
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    • 2019
  • In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

A Design of Digital CMOS X-ray Image Sensor with $32{\times}32$ Pixel Array Using Photon Counting Type (포톤 계수 방식의 $32{\times}32$ 픽셀 어레이를 갖는 디지털 CMOS X-ray 이미지 센서 설계)

  • Sung, Kwan-Young;Kim, Tae-Ho;Hwang, Yoon-Geum;Jeon, Sung-Chae;Jin, Seung-Oh;Huh, Young;Ha, Pan-Bong;Park, Mu-Hun;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1235-1242
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    • 2008
  • In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.

Photoelectrochemical Properties of a Cu2O Film/ZnO Nanorods Oxide p-n Heterojunction Photoelectrode for Solar-Driven Water Splitting (물분해용 Cu2O 박막/ZnO 나노막대 산화물 p-n 이종접합 광전극의 광전기화학적 특성)

  • Park, Junghwan;Kim, Hyojin;Kim, Dojin
    • Korean Journal of Materials Research
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    • v.28 no.4
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    • pp.214-220
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    • 2018
  • We report on the fabrication and photoelectrochemical(PEC) properties of a $Cu_2O$ thin film/ZnO nanorod array oxide p-n heterojunction structure with ZnO nanorods embedded in $Cu_2O$ thin film as an efficient photoelectrode for solar-driven water splitting. A vertically oriented n-type ZnO nanorod array was first prepared on an indium-tin-oxide-coated glass substrate via a seed-mediated hydrothermal synthesis method and then a p-type $Cu_2O$ thin film was directly electrodeposited onto the vertically oriented ZnO nanorods array to form an oxide semiconductor heterostructure. The crystalline phases and morphologies of the heterojunction materials were characterized using X-ray diffraction and scanning electron microscopy as well as Raman scattering. The PEC properties of the fabricated $Cu_2O/ZnO$ p-n heterojunction photoelectrode were evaluated by photocurrent conversion efficiency measurements under white light illumination. From the observed PEC current density versus voltage (J-V) behavior, the $Cu_2O/ZnO$ photoelectrode was found to exhibit a negligible dark current and high photocurrent density, e.g., $0.77mA/cm^2$ at 0.5 V vs $Hg/HgCl_2$ in a $1mM\;Na_2SO_4$ electrolyte, revealing an effective operation of the oxide heterostructure. In particular, a significant PEC performance was observed even at an applied bias of 0 V vs $Hg/HgCl_2$, which made the device self-powered. The observed PEC performance was attributed to some synergistic effect of the p-n bilayer heterostructure on the formation of a built-in potential, including the light absorption and separation processes of photoinduced charge carriers.