• Journal of the Korea Organic Resources Recycling Association
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• v.21 no.3
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• pp.74-81
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• 2013

In this study, the separation efficiency of wind power selector (the direction of the air flow of the air to perform gravity separation method) of municipal solid waste which was landfilled was investigated to reduce amount of waste that is designed to increase the recycling rate of wastes for the ANSYS CFX Program's numerical methods with wind through the separator. When a suction device designed to suction 1000mL of a plastic bag, the separation efficiency was 100% and when the wind speed was 0.9 m /sec or more and when the wind speed was 1.6 m / sec or more, the efficiency of plastic bottles in a mixture of 500mL and 1500mL plastic bottle waste was 100% and the aluminum screening efficiency of 250mL aluminum can was 100 % when the wind speed was 2.3 m / sec. In the last, 5mm thick compressed aluminum can efficiency was 90 % when the wind speed was 2.4 m / sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5C
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• pp.519-533
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• 2006

The number of channels specified in IEEE 802.15.4 Low-Rate Wireless Personal Area Networks(LRWPANs) is too few to operate many applications of WPANs in the same area. To overcome this limit, we introduce Virtual Channel, a novel concept to increase the number of available channels when various WPAN applications coexist. Basically, a virtual channel is a newly-created channel via superframe scheduling within the inactive period of a logical channel preoccupied by other WPANs. To maximize the coexistence capability of WPANs using virtual channels, we propose Least Collision superframe scheduler(LC-scheduler), its less complex heuristics both for a given single channel, and Virtual Channel Selector(VCS) to efficiently manage multiple available logical channels. In addition, a simple but practical synchronization method is developed to compensate different time drifts among coexisting WPANs. The simulation results demonstrate that a remarkable improvement on the coexistence capability of the 802.15.4 can be achieved through the proposed schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.104-111
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• 2002

In this paper, we proposed the architecture of the decoder which implements the multi-view images decoding algorithm. The study of the hardware structure of the multi-view image processing has not been accomplished. The proposed multi-view images decoder operates in a three stage pipelined manner and extracts the depth of the pixels of the decoded image every clock. The multi-view images decoder consists of three modules, Node selector which transfers the value of the nodes repeatedly and Depth Extractor which extracts the depth of each pixel from the four values of the nodes and Affine transformer which generates the projecting position on the image plane from the values of the pixels and the specified viewpoint. The proposed architecture is designed and simulated by the Max+plus II design tool and the operating frequency is 30MHz. The image can be constructed in a real time by the decoder with the proposed architecture.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.307-307
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• 2014

정보화 시대로 접어들면서 동일한 공간에 더 많은 정보를 저장할 수 있고, 보다 빠른 동작이 가능한 비휘발성 메모리 소자에 대한 요구가 증가하고 있다. 하지만, 최근 비휘발성 메모리 소자 관련 연구보고에 따르면, 메모리 소자의 소형화 및 직접화 측면에서, 전하 저장을 기반으로 하는 기존의 Floating-Gate(FG) Flash 메모리는 20 nm 이하 공정에서 한계가 예측 되고 있다. 따라서, 이러한 FG Flash 메모리의 한계를 해결하기 위해, 기존에 FET 기반의 FG Flash 구조와 같은 3 terminal이 아닌, Diode와 같은 2 terminal로 동작이 가능한 ReRAM, PRAM, STT-MRAM, PoRAM 등 저항변화를 기반으로 하는 다양한 종류의 차세대 메모리 소자가 연구되고 있다. 그 중, 저항 변화 메모리(ReRAM)는 CMOS 공정 호환성, 3D 직접도, 낮은 소비전력과 빠른 동작 속도 등의 우수한 동작 특성을 가져 차세대 비휘발성 메모리로 주목을 받고 있다. 또한, 상하부 전극의 2 terminal 만으로 소자 구동이 가능하기 때문에 Passive Crossbar-Array(CBA)로 적용하여 플래시 메모리를 대체할 수 있는 유력한 차세대 메모리 소자이다. 하지만, 이를 현실화하기 위해서는 Passive CBA 구조에서 발생할 수 있는 Read Disturb 현상, 즉 Word-Line과 Bit-Line을 통해 선택된 소자를 제외하고 주변의 다른 소자를 통해 흐르는 Sneak Leakage Current(SLC)를 차단하여 소자의 메모리 State를 정확히 sensing하기 위한 연구가 선행 되어야 한다. 따라서, 현재 이러한 이슈를 해결하기 위해서, 많은 연구 그룹에서 Diodes, Threshold Switches와 같은 ReRAM에 Selector 소자를 추가하는 방법, 또는 Self-Rectifying 특성 및 CRS 특성을 보이는 ReRAM 구조를 제안 하여 SLC를 차단하고자 하는 연구가 시도 되고 있지만, 아직까지 기초연구 단계로서 아이디어에 대한 가능성 정도만 보고되고 있는 현실 이다. 이에 본 논문은 Passive CBA구조에서 발생하는 SLC를 해결하기 위한 새로운 아이디어로써, 본 연구 그룹에서 선행 연구로 확보된 안정적인 저항변화 물질인 SiN를 정류 특성을 가지는 n-Si/Ti 기반의 Schottky Diode와 결합함으로써 기존의 CBA 메모리의 Read 동작에서 발생하는 SLC를 차단 할 수 있는 1SD-1R 구조의 메모리 구조를 제작 하였으며, 본 연구 결과 기존에 문제가 되었던 SLC를 차단 할 수 있었다.

• Journal of the Korean Chemical Society
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• v.46 no.5
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• pp.412-429
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• 2002

Chiral separation of gemifloxacin, an quinolone antibacterial agent, using (+)-(18-crown-6)-tetracar-boxylic acid $(18C6H_4)$ as a chiral selector was performed by capillary electrophoresis (CE). Direct analysis of quinolone antibacterial agent in body fluid is beneficial in terms of fast analysis time, multicomponent analysis. However, high con-centration of sodium ion in body fluid can prevent gemifloxacin from interacting with $18C6H_4$ since sodium ion has high affinity with $18C6H_4$ due to the strong charge interaction. Ethylenediaminetetraacetic acid (EDTA), as a chelating ligand, was added in the running buffer in order to reduce the interaction between sodium ion and the chiral selector. Increased separation efficiency and reduced migration time were observed while sodium ion exists in the sample solution at the concentration up to 150 mM.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.1
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• pp.12-17
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• 1975

This paper describes a new simplified logarithmic counting Tatemeter for the measurement of wide range counting rates without selector switch. Theoritical analysis of the proposed circuit and synthesis technique for designing a multi.decade instrument using this configuration are given. It has a linear response on the logarithmic scale for random pulses of Poisson's distribution as well as for periodic pulses. The experimental circuit designed by the proposed technique has a good logarithmic response over 5 decades covering the counting rates from 1 pps to $10^5$ pps. Also the causes of inaccuracy in the low and high range are examined and effestively removed.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1684-1692
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• 2016

In order to adapt the fast dynamic performances of Buck DC/DC converter, and reduce the influence on converter performance owing to uncertain factors such as the disturbances of parameters and load, a control strategy based on two-dimensional hybrid cloud model is proposed. Firstly, two cloud models corresponding to the specific control inputs are determined by maximum determination approach, respectively, and then a control rule decided by the two cloud models is selected by a rule selector, finally, according to the reasoning structure of the rule, the control increment is calculated out by a two-dimensional hybrid cloud decision module. Both the simulation and experiment results show that the strategy can dramatically improve the dynamic performances of the converter, and enhance the adaptive ability to resist the random disturbances, and its control effect is superior to that of the current-mode control.

• Proceedings of the KSME Conference
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• 2004.11a
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• pp.1288-1293
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• 2004

Inverse radiation problems are solved for estimating the boundary conditions such as temperature distribution and wall emissivity in axisymmetric absorbing, emitting and scattering medium, given the measured incident radiative heat fluxes. Various regularization methods, such as hybrid genetic algorithm, conjugate-gradient method and Newton method, were adopted to solve the inverse problem, while discussing their features in terms of estimation accuracy and computational efficiency. Additionally, we propose a new combined approach of adopting the genetic algorithm as an initial value selector, whereas using the conjugate-gradient method and Newton method to reduce their dependence on the initial value.