• 한국진공학회지
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• 제11권1호
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• pp.16-21
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• 2002

$Si_2H_6$가스를 이용한 LPCVD내에서의 실리콘의 선택적 에피텍시 성장을 $1000^{\circ}C$ 이하의 초청정 분위기하의 저온에서 수행하였다. HCI 첨가없이 초청정 공정으로 인한 양질의 에피텍시 Si층이 균일하게 얻어 졌으며, $SiO_2$위에 증착된 실리콘의 잠복기를 발견할 수 있었다. 단결정위의 에피텍시 층은 산화물 층위 보다 더 두껍게 증착되었다. 산소첨가로 잠복기가 20~30초간 증가하였다. 증착된 박막의 절단면과 표면 형상은 SEM으로 관찰되었으며, XRD를 통해 막질을 평가하였다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 춘계 학술발표강연 및 논문개요집
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• pp.14-14
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• 2002

• 한국재료학회:학술대회논문집
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• 한국재료학회 1992년도 추계학술발표강연 및 논문개요집
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• pp.46-47
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• 1992

• 한국재료학회지
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• 제12권5호
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• pp.363-368
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• 2002

we proposed the use of $Si_2H_ 6/H_2$ chemistry for selective silicon epitaxy growth by low-pressure chemical vapor deposition(LPCVD) in the temperature range $600~710^{\circ}C$ under an ultraclean environment. As a result of ultraclean processing, an incubation period of Si deposition only on $SiO_2$ was found, and low temperature epitaxy selective deposition on Si was achieved without addition of HCI. Total gas flow rate and deposition pressure were 16.6sccm and 3.5mtorr, respectively. In this condition, we selectively obtained high-quality epitaxial Si layers of the 350~1050$\AA$ thickness. In older to extend the selectivity, we kept high pressure $H_2$ environment without $Si_2H_6$ gas for few minutes after first incubation period and then we conformed the existence of second incubation period.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 2000년도 Proceedings of 2000 International Nano Crystals/Ceramics Forum and International Symposium on Intermaterials
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• pp.87-125
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• 2000

A new paradigm of crystal growth was suggested in a charged cluster model, where charged clusters of nanometer size are suspended in the gas phase in most thin film processes and are a major flux for thin film growth. The existence of these hypothetical clusters was experimentally confirmed in the diamond and silicon CVD processes as well as in gold and tungsten evaporation. These results imply new insights as to the low pressure diamond synthesis without hydrogen, epitaxial growth, selective deposition and fabrication of quantum dots, nanometer-sized powders and nanowires or nanotubes. Based on this concept, we produced such quantum dot structures of carbon, silicon, gold and tungsten. Charged clusters land preferably on conducting substrates over on insulating substrates, resulting in selective deposition. if the behavior of selective deposition is properly controlled, charged clusters can make highly anisotropic growth, leading to nanowires or nanotubes.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권3호
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• 반도체디스플레이기술학회지
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• 제15권1호
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• pp.41-46
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• 2016

In this study, gas flow and temperature distribution in the multi-wafer planetary CVD reactor for the Si epitaxial growth were analyzed. Although the structure of the reactor was simplified as the first step of the study, the three-dimensional analysis was performed taking all these considerations of the revolution of the susceptor and the rotation of satellites into account. From the analyses, a reasonable velocity field and temperature field were obtained. However, it was found that analyses including the upper structure of the reactor were required in order to obtain more realistic temperature results. DCS mole fraction above the satellite surface and the susceptor surface without satellite was compared in order to check the gas species mixing. We found that satellite rotation helped gases to mix in the reactor.

• 한국재료학회지
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• 제17권5호
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• pp.273-277
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• 2007

Vertically aligned Zinc Oxide rod arrays were grown by the self-assembly hydrothermal process on the GaN epitaxial layer which has a same lattice structure with ZnO. Zinc nitrate and DETA solutions are used in the hydrothermal process. The $(HfO_2)$ thin film was deposited on GaN and the patterning was made by the photolithography technique. The selective growth of ZnO rod was achieved with the patterned GaN substrate. The fabricated ZnO rods are single crystal, and have grown along hexagonal c-axis direction of (002) which is the same growth orientation of GaN epitaxial layer. The density and the size of ZnO rod can be controlled by the pattern. The optical property of ordered array of vertical ZnO rods will be discussed in the present work.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.471-475
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• 2000

P-type (100) Si wafer patterned with 1000$\AA$ SiO$_2$island was used as substrate and the Si films were deposited under low pressure using Si$_2$H$_{6}$-H$_2$gas mixture where the total gas flow rate and deposition pressure were 16.6sccm and 3.5mtorr, respectively. In this condition, we selectively obtained high-quality epitaxial Si layer of the 350~1050$\AA$ thickness. In order to extend the incubation period, we kept high pressure H$_2$ environment without Si$_2$H$_{6}$ gas for few minutes after first incubation period and then we conformed the existence of second incubation period.iod.

• ETRI Journal
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• 제26권6호
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.