• Journal of the Korean Society for Precision Engineering
• /
• v.14 no.11
• /
• pp.102-109
• /
• 1997

A two-degree-of freedom (TDF) $H_{\infty}$controller for a seeker scan loop is presented for the purpose of improving scanning performances. The perturbed plant model is characterized via the normalized coprime factorization. The TDF $H_{\infty}$controller is designed based on the loop shaping design procedure and model matching approach, and its performances are evaluated and compared with those of a previous work. It is demonstrated that the proposed TDF $H_{\infty}$controller is more effective to the control of the seeker scan loop than the previous controller.oller.

• Proceedings of the IEEK Conference
• /
• 2002.06d
• /
• pp.81-84
• /
• 2002

This paper presents the real-time PCB(Printed circuit board) inspection system that can detect thin open/short error using the line scan camera. After a overall introduction of our system, the outline of our inspection methods are described. The goal of our inspection system is the real time and detailed inspection using the line scan camera. To perform inspection processing in real-time, we utilize double buffering structure. In order to solve the problem of unexpectable pixels of PCB, we propose melting process which eliminates unexpectable pixels of PCB. The design and development of our prototype of PCB ins- pection system is discussed and test results are presented to show the effectiveness of the developed inspection algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.43 no.5
• /
• pp.466-471
• /
• 2015

In this paper, the design technique of the wide swath TOPS(Terrain Observation by Progressive Scan) imaging mode is introduced. The TOPS mode overcomes the scalloping limitations imposed by ScanSAR mode by steering the antenna pattern along track direction during the acquisition of a burst. This paper reports the operation concept of TOPS imaging and mode design result to extract the SAR operational parameters. Finally, several analyzed results such as IRF(Impulse Response Function), NESZ(Noise Equivalent Sigma Zero) and DTAR(Distributed Target Ambiguity Ratio) are presented.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.8
• /
• pp.1024-1030
• /
• 1999

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 UpdateDR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2 log(n+2) 의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.Abstract IEEE 1149.1 Boundary-Scan is a testable design technique for the detection and diagnosis of faults on a board. However, since it takes 2.5TCKs to observe data launched from an output boundary scan cell due to inherent characteristics of the TAP controller, it is impossible to test delay defects on the interconnect nets. This paper introduces a new technique that postpones the activation of UpdateDR signal by 1.5 TCKs while complying with IEEE 1149.1 standard. Furthermore we have developed 2 log(n+2) , where N is the number of nets, interconnect test patterns to test delay faults in addition to the static interconnect faults. The validness of our approach is verified through the design and simulation.

• The KIPS Transactions:PartC
• /
• v.9C no.3
• /
• pp.359-366
• /
• 2002

Nowadays, the hacking techniques are developed increasingly with wide use of internet. The recent type of scanning attack is appeared in against with multiple target systems on the large scaled domain rather than single network of an organization. The development of scan detection management system which can detect and analyze scan activities is necessary to prevent effectively those attacking at the central system. The scan detection management system is useful for effective utilization of various detection information that received from scan detection agents. Real time scan detection management system that can do the integrated analysis of high lever more that having suitable construction in environment of large scale network is developed.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.10
• /
• pp.728-734
• /
• 2001

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.11
• /
• pp.54-61
• /
• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for controller circuits is proposed. The proposed method always guarantees a short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The proposed method also shortens the test application time through a test pattern re-ordering procedure. The efficiency of the proposed method is demonstrated using well known MCNC'91 FSM benchmark circuits.

• The Journal of Korean Academy of Prosthodontics
• /
• v.57 no.4
• /
• pp.425-431
• /
• 2019

This clinical case report describes the digital workflow that combines a face scan, cone beam computed tomography and an intraoral scan to visualize the outcome of prosthodontic treatment in the anterior region. This approach improves communication between clinic, laboratory and patients. A patient with healthy general condition came for a restorative treatment to treat post-traumatic central incisors of maxilla. A virtual patient replica was made by incorporating a face scan, cone beam computed tomography and an intraoral scan. Design mockup of definitive restorations was shown to the patient and modified according to the patient's desire. This digital workflow facilitates the fabrication of optimal esthetic restorations, and enhances the predictability of outcome of restorations.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.1963-1964
• /
• 2008

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. We propose a new technique to re-design about clock operation. This technique propose about low power operation of scan clock and saved time of test operation.

• Fashion & Textile Research Journal
• /
• v.24 no.4
• /
• pp.443-450
• /
• 2022

This study developed a three-dimensional helmet mold design software that can design helmets for treating the infant plagiocephaly (flat head syndrome) using three-dimensional head scan data. For this, the three-dimensional head data of sixth SizeKorea body measurement project as well as the data produced by a head modeling software were used to prepare the head shape data of plagiocephaly patients. A total of 14 landmarks and 10 dimensions of heads required for helmet mold shape design and plagiocephaly diagnosis were automatically measured using an anthropometric analysis software. Using the software developed in this study, plagiocephaly can be diagnosed not only visually by three-dimensional head data visualization but also quantitatively by calculating the medically defined indices such as cranial index, which measures the proportions of the head, and the cranial vault asymmetry index, which measures the asymmetry of the head. The basic shape of the helmet mold was automatically generated based on the head scan data. Additionally, it is possible to fine tune the shape of the mold to reflect individual characteristics by using a free form deformation technique. Finally, the designed helmet mold was converted into the data that can be printed on a three-dimensional printer for generating the actual prototype.