• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.11-20
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• 1998

Testability analysis computes controllabilities and observabilities of all lines of a circuit and then evaluates fault coverage. The values of controllability and observability as well as fault coverage produced by testability analysis are used for applications of testability analysis. ITEM was evaluated as a fault coverage tool. But the values of controllability and observability at all lines of circuits must be estimated as a performance measure of testability tools for another application such as partial scan. In this paper, partial scan method based on sensitivity analysis which estimates relative improvement of detectability of circuits after scanning a flip-flop is used for performance evaluation of ITEM. Performance of ITEM, with respect to testability values on each net, has been measured by comparing ITEM and STAFAN. Partial scan performance achieved by ITEM is very similar to that of STAFAN, but ITEM takes less CPU time. Therefore ITEM is very efficient for partial scan application because ITEM runs faster for very large circuits in which execution time is critical.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.572-580
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• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.793-799
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• 2016

A multi-purpose sensor interface that provides dual-mode operation of fingerprint sensing and physiological signal detection is presented. The dual-mode sensing capability is achieved by utilizing inter-pixel shielding patterns as capacitive amplifier's input electrodes. A prototype readout circuit including a fingerprint panel for feasibility verification was fabricated in a $0.18{\mu}m$ CMOS process. A single-channel readout circuit was implemented and multiplexed to scan two-dimensional fingerprint pixels, where adaptive calibration capability against pixel-capacitance variations was also implemented. Feasibility of the proposed multi-purpose interface was experimentally verified keeping low-power consumption less than 1.9 mW under a 3.3 V supply.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.10
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• pp.14-22
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• 2010

The most costly and time-consuming process in the fabrication of today's multi-layer circuit board is drilling interconnection holes between adjacent layers and via holes within a layer. Decreasing size of via holes being demanded and growing number of via holes per panel increase drilling costs. Component density and electronic functionality of today's multi-layer circuit boards can be improved with the introduction of cost-effective, variable depth laser drilled blind micro via holes, and interconnection holes. Laser technology is being quickly adopted into the circuit board industry but can be accelerated with the introduction of a true production laser drilling system. In order to get optimized condition for drilling to FPCB (Flexible Printed Circuit Board), we use various drill pattern as drill step. For productivity, we investigate drill path optimization method. And for the precise drilling the thermal drift of scanner and temperature change of scan system are tested.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.48-51
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• 1997

This paper presents the algorithm of FIC inspection in chip mounter. When device is mounted on the PCB, it is impossible to get zero defects since there are many problems which can not be predicted. Of these problems, devices with bent corner leads due to mis-handling and which are not placed at a given point measured along the axis are principal problem in SMT(Surface Mounting Technology). In this paper, we proposed a new algorithm based on the Radon transform which uses a projection to inspect the FIC(Flat Integrated Circuit) device and compared this method with other algorithms. We measured the position error and applied this algorithm to our image processing board which is characterized by line scan camera. We compared speed and accuracy in our board.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.71-78
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• 2013

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.12
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• pp.586-593
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• 1986

Ringing during the scan time deteriorates the picture quality of television receiver. By tuning the stray reactance of the flyback transformer(FBT)to harmonics of the retrace pulse, the ringing can be suppressed and this is, what is called, the harmonic tuning methed. But finding the conditions for the ringing to cease in lossy FBT and satisfying these conditions at design stage require much time and experience. In this paper, the conditions for the ringing to cease in loss-included equivalent circuit are derived and a new method, unharmonic-tuning method, is suggested.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2001.05a
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• pp.209-216
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• 2001

A key advantage of boundary scan technology is the ability to observe data at device inputs and control data at device outputs, independent of on-chip system logic. But, this method has a disadvantage for detecting of faults that changes their states very fast. We present a method to solve this problem and make it possible to detect the signals. We shown the simulation results of testing a circuit that has fast signal above the clock speed.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.732-736
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• 2005

Discussion of this study is that a horizontal deflection system satisfactory of operating at horizontal scan rates from 30KHz to 50KHz has been developed. It will be used in the large-area, color, high-resolution and multi-sync rear-projection CRT display device. Its characters, including the description, analysis and deflection circuit loss, are presented.