• 분석과학
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• 제25권2호
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• pp.91-101
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• 2012

2010년부터 지정악취물질로 관리 중인 유기지방산은 큰 반응성과 그에 따른 낮은 회수율 등의 문제로 인해, 분석이 난해한 성분으로 알려져 있다. 악취공정시험기준에서는 대기 중에 존재하는 유기지방산을 분석하는 방법으로 알칼리함침필터법과 알칼리흡수용액법을 제시하고 있다. 본 연구에서는 유기지방산의 분석기법을 전반적으로 비교검토하였다. 그러나 이들 지정분석방법에 대한 객관적인 검증이 쉽지않다는 점을 감안할 때, 유기지방산의 새로운 대안 분석방안으로 고체흡착관-저온농축탈착법 등을 고려할 필요가 있다. 고체흡착관으로 시료를 채취하고 저온농축열탈착기를 이용하여 분석할 경우, 공정시험기준상에 제시한 분석방법들에 비해 상당히 간편하고 검정이 용이하다는 이점이 있다. 본 연구에서는 이러한 분석방법에 대한 고찰에 덧붙여, 표준시료의 준비, 시료의 채취단계, 최종적인 검출단계에 대한 부분에 대해서도 검토하였다. 유기지방산의 현장시료를 채취 및 분석하기 위해서, 용기채취법의 적용은 심각한 오차를 수반할 수 있다는 점을 확인하였다. 또한 현장에서 채취한 시료의 유기지방산을 분석할 때, GC/FID에 의존할 경우, 여러 가지 간섭 성분의 영향을 배제하기 어렵다. 따라서 유기지방산의 분석에는 GC/MS를 이용하여 정량뿐 아니라 정성적인 부분까지 동시에 검토하는 것이 중요하다.

• 통합자연과학논문집
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• 제7권3호
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• pp.208-213
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• 2014

National-wide and/or large scale sample surveys generally use complex sample design. Traditional Pearson chi-square test is not appropriate for the categorical complex sample data. Rao-Scott suggested an adjustment method for Pearson chi-square test, which uses the average of eigenvalues of design matrix of cell probabilities. This study is to compare the efficiency of Rao-Scott first order adjusted test to Wald test for homogeneity between two populations using 2009 Gyeongnam regional education offices's customer satisfaction survey (2009 GREOCSS) data. The 2009 GREOCSS data were collected based on stratified three-stage cluster sampling with probability proportional to size. The empirical results show that the Rao-Scott adjusted test statistic using only the variances of cell probabilities is very close to the Wald test statistic, which uses the covariance matrix of cell probabilities, under the 2009 GREOCSS data based. However it is necessary to be cautious to use the Rao-Scott first order adjusted test statistic in the place of Wald test because its efficiency is decreasing as the relative variance of eigenvalues of the design matrix of cell probabilities is increasing, specially more when the number of degrees of freedom is small.

• The Journal of Asian Finance, Economics and Business
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• 제8권3호
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• pp.497-504
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• 2021

This extended study aims to analyze empirically the influence of firm diversification on firm performance moderated by the stages of the firm life cycle, which consists of introduction, growth, maturity, and decline. The target population of this study is the firms listed on the Indonesian Stock Exchange. The sampling method uses purposive sampling in the multi-business firm in Indonesia; it includes as many as 127 firms over the period from 2011 to 2017, totaling 889 firm-year observations. The firm performance is measured using a return of equity while the level of firm diversification with the minimum number of two operating segments is proxied by the Herfindahl index. The analysis method used in this study is the estimator model of the Generalized Method of Moment (GMM). The main findings show that the firm life cycle at the stage of growth and maturity significantly strengthens the influence of firm diversification on firm performance. On the other hand, the stage of decline fails to moderate the relationship between firm diversification and firm performance. This study discusses the implications and contributions of the findings theoretically, and provide some policy justifications for potential investors before they invest their money in the capital market.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Korean Chemical Engineering Research
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• 제60권1호
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• pp.100-115
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• 2022

교대로 운전되는 광촉매반응기 공정 및 바이오필터 공정[전통적 바이오필터(L 반응기)와 두 개의 유닛(R_up 및 R_dn)을 가지는 개선된 바이오필터(R 반응기)]으로 구성된 통합 하이브리드시스템(통합처리시스템)에서 에탄올과 황화수소를 동시 함유한 폐가스 처리를 성공적으로 수행하였다. 통합처리시스템의 운전 단계로서 HA1, HA2 및 폐가스의 공급 방향이 뒤바뀐 HA3T stage의 광촉매 공정에서 각각 55, 50 및 45%의 에탄올 제거효율과 각각 70, 60 및 37%의 황화수소 제거효율을 보였다. 특히, HA3T stage에서 통합처리시스템으로 공급되는 폐가스(feed)의 황화수소 농도가 10 ppmv에서 20 ppmv로 급증함에 따른 황화수소 부하량의 증가로 인하여 특히 황화수소 제거효율의 급격한 감소를 관찰하였다. 통합처리시스템의 HA1, HB1, HA2 및 HB2 stage 및 HA3T stage의 초반에, 개선된 바이오필터(R 반응기)의 각 유닛에 설치한 sampling 구들의 에탄올의 파과 순서 및 에탄올 처리효율의 크기 순서는, HA3T stage 후반과 HB3T stage의 경우에서 각각 거꾸로 바뀌었다. 한편 개선된 바이오필터(R 반응기)에서 황화수소의 경우는 파과 정도가 에탄올의 경우만큼 두드러지지는 않았으나 비슷한 추세가 관찰되었다.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• 한국전산구조공학회논문집
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• 제31권3호
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• pp.141-145
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• 2018

본 논문에서는 이단계 칼만필터를 활용한 구조물의 3 자유도 동적변위 계측 시스템을 소개한다. 개발 시스템은 센서 모듈, 베이스 모듈, 컴퓨테이션 모듈로 구성되어 있다. 센서 모듈은 100Hz 샘플주파수의 고정밀 가속도를 계측하는 포스피드백 가속도계와 10Hz의 샘플주파수의 저정밀도의 속도, 변위를 계측하는 저가의 RTK-GNSS로 구성되어 있다. 계측된 데이터는 LAN 케이블을 통하여 컴퓨테이션 모듈로 전송되고, 컴퓨테이션 모듈에서 이단계 칼만필터를 활용하여 100Hz 샘플주파수의 고정밀 변위를 실시간으로 산정한다. 개발 시스템의 변위 계측 정밀도를 검증하기 위해 미국, 캘리포니아에 위치한 San Francisco-Oaklmand Bay bridge 에서 현장 실험을 수행하였으며, 실험 결과 1.68mm RMS 오차를 보임을 확인하였다.

• 품질경영학회지
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• 제33권4호
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• pp.88-95
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• 2005

Multistage screening is a common practice when a component has a critical effect on the function of the assembly. A defect in a component might incur malfunction of an electronic device, resulting in a great amount of loss. Multistage screening, including duplicated screening inspections, may provide a good solution for this problem when inspection errors are present. In the company studied here, the manufacturing process of the multiple layer chip capacitor includes two-stage screening. In the first stage, screening inspection is performed repeatedly until no defects are found in the lot. In the second stage, sampling inspection is performed by a group of experts prior to shipment. In this article, we review the procedure used in the field and suggest a revised model of the multiple screening procedure and solution method for this situation. The usefulness of the proposed model is discussed through a practical example.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1197-1200
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• 2003

This paper presents A/D converter for the signal processing of infrared sensor and CMOS image sensor. The A/D converter designed in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW at 2.5V supply voltage. This A/D converter is based on a pipeline architecture in which the number of bits converted per stage and the stage number are optimized to achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권3호
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• pp.186-190
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• 2005

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics, 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB\~-0.63LSB$ and $0.53LSB\~-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.