• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.10
• /
• pp.1832-1837
• /
• 2011

The fault current has increased due to the large power demand in power distribution system and network distribution system. To protect the power system effectively from the increased fault current, the superconducting fault current limiter (SFCL) has been notified. However, the conventional SFCL has some problems such as cost, operation, recovery, loss. To solve some problems, the hybrid superconducting fault current limiter using the fast switch was proposed. However, hybrid SFCL also has a problem that is protection coordination in power distribution system with hybrid SFCL. In this paper, the fault current limiting characteristics of hybrid SFCL with first half cycle non-limiting operation according to the fault angle, the resistance of superconducting element, and the magnitude of Current Limit Resistor (CLR) which are the components of hybrid SFCL were analyzed through the experiments.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.562-568
• /
• 2013

This paper presents a design of a wireless power transfer system based on magnetic resonant coupling technology with in-band wireless communication. To increase the transmission distance and compensate for the change in the effective capacitance due to the varying distance, the proposed system used a loop antenna with a selectable capacitor array. Because the increased transmission distance enables multiple charging, we added a communication protocol operated at the same frequency band to manage a network and control power circuits. In order to achieve the efficient bandwidth in both power transfer mode and communication mode, the S-parameters of the loop antennas are adjusted by switching a series resistor. Our test results showed that the loop antenna achieved a high Q factor in power transfer mode and enough passband in communication mode.

• Proceedings of the KIEE Conference
• /
• 1996.07c
• /
• pp.1819-1821
• /
• 1996

A compact size high voltage pulse generator with nanosecond rise time has been fabricated and investigated experimentally. It can be reduced the inductance of the generator by fixing the Marx generator components and pulse forming network components into a single cylindrical unit. As a result, it can be obtained nanosecond rise time about $8{\sim}10[ns]$ and pulse width of several hundred nanoseconds from the modified Marx pulse generator. And parametric studies showed that the rise time of the output pulse was depended little on the change of the load resister and the charging capacitor while the pulse width of the output pulse was depended greatly upon the change of the load resistor and the charging capacitor.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.68-74
• /
• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.2 s.117
• /
• pp.213-218
• /
• 2007

In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.

• Journal of Advanced Marine Engineering and Technology
• /
• v.33 no.8
• /
• pp.1239-1245
• /
• 2009

Currently, so many approaching methods are being developed to optimize the antenna size. In this paper, We fabricated Inverted-F type antenna attaching lumped components to solve the limitation of antenna size. Through experiments, a basic Inverted-F type antenna was fabricated and satisfied the adequate radiation pattern. After this, we researched the effect of antenna varied by matching circuit consist of chip type resistor, inductor, and capacitor. Using that elements, the antenna was matched at aim frequency. The proposed antenna's size is $7\;{\times}\;24\;mm$ that is very small size against the resonance frequence. Measuring the developed antenna, Its return loss was -18dB. Thus, this antenna can be used for Z-wave systems.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.15 no.6
• /
• pp.20-26
• /
• 2001

In this paper, we design tunnel inner section displacement measurement system which is composed of potentiometer-type displacement sensors, microcontroller-based intelligent sensing head and host computer for the management system and acquisition data. Multiple node communication bus connects the intelligent sensing heads with the host computer. For safe and re1iab1e network operation we use daisy-chain configuration, termination resistor, fail-safe biasing circuit. For tole enhancement of system utilization, we use modbus protocol. The acquisition data are transmitted to host computer and managed by database. Several data request conditions and sorting conditions are provided by management software. The utilization of designed system is confirmed by experiment.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.6
• /
• pp.2178-2186
• /
• 2018

Online identification of load parameters is the premise of establishing a stable and highly-efficient ICPT (Inductive Coupled Power Transfer) system. However, compared with pure resistive load, precise identification of composite load, such as resistor-inductance load and resistance-capacitance load, is more difficult. This paper proposes a method for detecting the composite load parameters of ICPT system utilizing harmonics. In this system, the fundamental and harmonic wave channel are connected to the high frequency inverter jointly. The load parameter values can be obtained by setting the load equation based on the induced voltage of secondary-side network, the fundamental wave current, as well as the third harmonic current effective value received by the secondary-side current via Fourier decomposition. This method can achieve precise identification of all kinds of load types without interfering the normal energy transmission and it can not only increase the output power, but also obtain higher efficiency compared with the fundamental wave channel alone. The experimental results with the full-bridge LCCL-S type voltage-fed ICPT system have shown that this method is accurate and reliable.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.2
• /
• pp.184-191
• /
• 1993

Continuous-time integrated filters, implemented in MOS VLSI technology, have been receiving considerable attention. In this paper, a continuous-time fifth order elliptic low-pass MOSFET-C filter has been designed with a cutoff frequency 3,400Hz. First an active RC filter is designed using cascade method which each block can be tunable. And then the resistors of an active RC network are replaced by a linear resistor using NMOS depletion transistors operated in the triode region. This continuous-time MOSFET filter have simpler structure than switched-capacitor filter, so reduce the chip area. The designed MOSFET-C filter characteristics are simulated by PSPICE program.

• ETRI Journal
• /
• v.33 no.6
• /
• pp.897-903
• /
• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.