• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.454-460
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• 2003

In this paper, we present a novel method of parallelization of the modular multiplication algorithm to improve time and space complexity on RNS (Residue Number System). The parallel algorithm executes modular reduction using new table lookup based reduction method. MRS (Mixed Radix number System) is used because algebraic comparison is difficult in RNS which has a non-weighted number representation. Conversion from residue number system to certain MRS is relatively fast in residue computer. Therefore magnitude comparison is easily Performed on MRS. By the analysis of the algorithm, it is known that it requires only 1/2 table size than previous approach. And it requires 0(ι) arithmetic operations using 2ㅣ processors.

• The Journal of Information Technology
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• v.12 no.2
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• pp.39-47
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• 2009

Residue Number System is used for the purpose of increasing the speed of processing in the many application parts of Image Processing, Computer Graphic, Neural Computing, Digital Signal Processing etc, since it has the characteristic of parallelism and no carry propagation at each moduli. DRNS has the twice RNS Conversion, it is used to decreases the size of the operator in RNS. But it has a week point on the Second Residue to First Residue Conversion time. So, in this paper SRTFR(Second Residue to First Residue) Converter using MRC(Mixed Radix Conversion) is designed to decrease the size of RTB(Residue to Binary) Converter. Since the proposed SRTFR Converter using MRC(Mixed Rdix Convertion) has a pipeline processing. Also, modular operation is applied to at each partitioned SAM(Subtraction and Addition) and MA(Multiplication and addition). In the following study, the more effective design on MA is needed.

• ETRI Journal
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• v.38 no.2
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• pp.326-336
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• 2016

We propose and describe new error control algorithms for redundant residue number systems (RRNSs) and residue number system product codes. These algorithms employ search techniques for obtaining error values from within a set of values (that contains all possible error values). For a given RRNS, the error control algorithms have a computational complexity of $t{\cdot}O(log_2\;n+log_2\;{\bar{m}})$ comparison operations, where t denotes the error correcting capability, n denotes the number of moduli, and ${\bar{m}}$ denotes the geometric average of moduli. These algorithms avoid most modular operations. We describe a refinement to the proposed algorithms that further avoids the modular operation required in their respective first steps, with an increase of ${\lceil}log_2\;n{\rceil}$ to their computational complexity. The new algorithms provide significant computational advantages over existing methods.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.25-37
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• 1996

To process computer graphics in real time, the high-speed operations(multiplier and adder) are needed to increase the speed of graphic process. RNS(Residue Number System) is integer number system that has the parallel and high-speed operation. Also, it is able to design both high-speed multiplier and adder, since a cyclic group has an isomorphic relation between multiplication and addition in RNS. So in this paper, DRNS(Double Residue Number System) is proposed, it is used for the multiplier and the adder, which are designed using a circulative code for the high-speed graphic processor in RNS. The designed multiplier would operate with the speed of 87Mzz two TTL using 74s09 and 74s32.

• The Journal of Information Technology
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• v.2 no.2
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• pp.145-161
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• 1999

This paper proposes a high speed back propagation neural networks which uses the residue number system. making the high speed operation possible without carry propagation Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed, The Designed circuits are descripted by VHDL and synthesized by Compass tools. Result of simulations shows that critical path delay time is about 19nsec and the size can be reduced to 40% compared to the neural networks implemented by the real number operation unit. The proposed design circuits can be implemented in parallel distributed processing system with desired real time processing.

• Fisheries and Aquatic Sciences
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• v.22 no.12
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• pp.29.1-29.7
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• 2019

Veterinary drugs are widely used to protect production-related diseases and promote the growth of farmed fish. The use of large amounts of veterinary drugs may have potential risk and cause adverse effects on both humans and the environment. In this study, we developed risk-based ranking based on a scoring system to be applied in the national residue program. In this approach, the following three factors of veterinary drugs that may occur as residues in fishery products were considered: potency (acceptable daily intake), usage (number of dose and withdrawal period), and residue occurrence. The overall ranking score was calculated using the following equation: potency × usage (sum of the number of sales and withdrawal period) × residue occurrence. The veterinary drugs that were assigned high score by applying this approach were enrofloxacin, amoxicillin, oxolinic acid, erythromycin, and trimethoprim. The risk-based approach for monitoring veterinary drugs can provide a reliable inspection priority in fishery products. The developed ranking system can be applied in web-based systems and residuemonitoring programs and to ensure safe management of fishery products in Korea.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.69-76
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• 1993

In this paper we propose a design of a digital neuron processor using the residue number system for efficient matrix.vector multiplication involved in neural processing. Since the residue number system needs no carry propagation for modulus operations, the neuron processor can perform multiplication considerably fast. We also propose a high speed algorithm for computing the sigmoid function using the specially designed look-up table. Our method can be implemented area-effectively using the current technology of digital VLSI and siumlation results positively demonstrate the feasibility of our method. The proposed method would expected to adopt for application field of digital neural network, because it could be realized to currently developed digital VLSI Technology.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.662-665
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• 1988

This paper proposes the Minimum-Distance Classification(MDC) processor using the Residue Number System(RNS). The proposed MDC Processor in this paper is efficient for real-time pattern clustering application and illustrate satisfiable error rate in application experiments of image segmentation but error rate increase as cluster number do.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.6
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• pp.6-10
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• 1983

In this paper, an implementation method for digital filters using the residue arithmetic is proposed. This method can be used for processing digital signals with larger number of bits by applying the idea of the bit-slice algorithm, while previous residue digital filters can process digital signals with only a small number of bits. Furthermore, high-speed residue addition, subtrac-tion, and multiplication using look-up tables make it possible to get more flexible filters. Everything that is mentioned above is proved by implementing a cascade fourth-order Butterworth lowpass digital filter using this method.