• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Society of Naval Architects of Korea
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• v.57 no.4
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• pp.207-212
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• 2020

To decide a separation distance of the redundant vital equipment in a naval ship, the damage radius due to an aerial explosion should be estimated. In this research, a simplified formula for the damage radius has been developed by using existing empirical formulae for reflected shock pressure and shock lethality value of equipment. As a numerical example, the damage radius for a typical pump aboard a naval ship has been calculated by the developed formula and compared with the results calculated by Measure of Total Integrated Ship Survivability (MOTISS) which is one of survivability analysis codes verified, validated and accredited by the US Navy. Also, comparison with the results calculated by existing other simplified formulae has been made.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.

• Journal of the Society of Naval Architects of Korea
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• v.49 no.3
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• pp.254-263
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• 2012

The survivability of warship is assessed by susceptibility, vulnerability and recoverability. Essentially, a vulnerability assessment is a measure of the effectiveness of a warship to resist hostile weapon effects. Considering the shot line and its penetration effect on the warship, present study introduces the procedural aspects of vulnerability assessments of warship. Present study also considers the prediction of penetration damage to a target caused by the impact of projectiles. It reflects the interaction between the weapon and the target from a perspective of vulnerable area method and COVART model. The shotline and tracing calculation have been directly integrated into the vulnerability assessment method based on the penetration equation empirically obtained. A simplified geometric description of the desired target and specification of a threat type is incorporated with the penetration effect. This study describes how to expand the vulnerable area assessment method to the penetration effect. Finally, an example shows that the proposed method can provide the vulnerability parameters of the warship or its component under threat being hit through tracing the shotline path thereby enabling the vulnerability calculation. In addition, the proposed procedure enabling the calculation of the component's multi-hit vulnerability introduces a propulsion system in dealing with redundant Non-overlapping components.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.8-15
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• 2007

This paper proposed hardware architecture of the block cryptographic algorithm HIGHT aiming small size and low power application, and analyzed its performance. The HIGHT is a modified algorithm of the Feistel. The encryption and decryption circuit were designed as one iterative block. It reduces the redundant circuit that yields small area. For the performance improvement, the circuit generates 32-bit subkey during 1 clock cycle. we synthesized the HIGHT with Hynix $0.25-{\mu}m$ CMOS technology. The proposed circuit size was 2.658 EG(equivalent gate), and its power consumption was $10.88{\mu}W$ at 2.5V for 100kHz. It is useful for a passive RFID tag or a smart IC card of a small size and low power.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.396-405
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• 2009

An interlocking equipment of railway signalling systems should have very high functional safety and reliability properties because of its vital railway protection functionality. In order to achieve the required safety and reliability level, an engineer, in general, designs and implements the interlocking equipment to operate under RTOS(Realtime Operating System) environment, and the control hardware architecture redundant to cope with the random failures of system or subsystem. In such an architecture, it's very difficult to implement the interlocking equipment to communicate with various interface systems including the signal operator's terminal. In this paper, we propose a dual ethernet network topology and dual packet seamless transfer protocol algorithm for railway signaling system such as the interlocking equipment. We verify in this paper that the proposed DPST protocol algorithm has the evidence of its robust properties against the random hardware faults and communication errors. The proposed communication structure and algorithm is implemented in the electronic interlocking equipment for the private railway system of Hyundai Steel Company and its performance and properties are validated on the guideline of European Railway Standard EN50159.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.2
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• pp.66-74
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• 2008

Since modem embedded systems need to access, manipulate or store sensitive information, it requires being equipped with cryptographic file systems. However, cryptographic file systems result in poor performance so that they have not been widely adapted to embedded systems. Most cryptographic file systems degrade the performance unnecessarily because of system architecture. This paper proposes ISEA (Indexed and Separated Encryption Approach) that supports for encryption/decryption in system architecture and removes redundant performance loss. ISEA carries out encryption and decryption at different layers according to page cache layer. Encryption is carried out at lower layer than page cache layer while decryption at upper layer. ISEA stores the decrypted data in page cache so that it can be reused in followed I/O request without decryption. ISEA provides page-indexing which divides page cache into cipher blocks and manages it by a block. It decrypts pages partially so that it can eliminate unnecessary decryption. In synthesized experiment of read/write with various cache hit rates, it gives results suggesting that ISEA has improved the performance of encryption file system efficiently.

• Journal of Construction Engineering and Project Management
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• v.4 no.1
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• pp.8-14
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• 2014

The Construction industry in Yemen confronts many development constraints, such as the inadequate implementation of appropriate building materials and labour construction technologies. Thus, this research looks over building materials and labour construction technologies used on the local housing construction projects by verifying the percentage of construction expenditure consumed by the main construction components (Materials, Labour and Overhead and Profit), along with the implemented construction technologies. The paper conducts a survey to acquire the cost distribution of the construction main components. The outcomes of the survey were discussed; the discussion was supported by literature on similar issues from some countries. The outcomes confirmed the relatively limited percentage in labour cost and profit, and the elevated percentage of construction materials cost, which are because of the excessive and inappropriate use of materials. What's more, established that the excessively redundant unskilled labours are not effectively engaged in the construction activities, this is due to the tendency of the market in using labour-base technologies. This paper is to recommend a suitable policies and strategies has to be used to decrease cost by using efficiently appropriate construction practice and local materials, moreover take advantage of excessive labour to reduce unemployment.

• Journal of Korea Game Society
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• v.17 no.5
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• pp.103-112
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• 2017

In recent years, expansions and advances of the Internet of Things (IoTs) in a distributed MMOGs (massively multiplayer online games) architecture have resulted in massive growth of data in terms of server workloads. We propose a combing Sparse Autoencoder and one of platforms in MMOGs, ProGReGA. In the process of Sparse Autoencoder, data representation with respect to enhancing the feature is excluded from this set of data. In the process of load balance, the graceful degradation of ProGReGA can exploit the most relevant and less redundant feature of the data representation. We find out that the proposed algorithm have become more stable.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.615-618
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• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.