• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.5
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• pp.836-858
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• 2010

Web Services allow a user to integrate applications from different platforms and languages. Since mobile applications often run on heterogeneous platforms and conditions, Web Service becomes a popular solution for integrating with server applications. However, because of its verbosity, XML based SOAP messaging gives the possible overhead to the less powerful mobile devices. Based on the mobile client's behavior that it usually exchanges messages with Web Service continuously in a session, we design the Handheld Flexible Representation architecture. Our proposed architecture consists of three main components: optimizing message representation by using a data format language (Simple_DFDL), streaming communication channel to reduce latency and the Context-store to store context information of a session as well as redundant parts of the messages. In this paper, we focus on the Context-store and describe the architecture with the Context-store for improving the performance of mobile Web Service messaging. We verify our approach by conducting various evaluations and investigate the performance and scalability of the proposed architecture. The empirical results show that we save 40% of transit time between a client and a service by reducing the message size. In contrast to solutions for a single problem such as the compression or binarization, our architecture addresses the problem at a system level. Thus, by using the Context-store, we expect reliable recovery from the fault condition and enhancing interoperability as well as improving the messaging performance.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.85-88
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• 2000

Distributed Control System(DCS) is one of the best solutions to implement control systems because it provides continuous observation of control process and execution of commands to induce proper operations. In this paper, a design of control network for DCS in nuclear power plant is proposed. The proposed control network on DCS has a simple architecture and deterministic property. Thus, the proposed control network offers hard real-time periodic service. It also has redundant media for the fault-tolerance. As a result, high safety and reliability required in nuclear power plant are guaranteed.

• The KIPS Transactions:PartD
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• v.16D no.6
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• pp.881-888
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• 2009

This research introduces the architecture of managing products based software. There are many of the architectures for managing products using software instead of manpower. In case of MVC and existing architectures, The architectures transfer redundant data so the architectures cause a problem that unnecessary data moved. This research presents VMDC(View, Model, Dispatcher, Controller) architecture to solve the problem. Dispatcher of VMDC grasps necessary data and reconstructs objects to efficient transferring data. This research shows usecase that designed VMDC(View, Model, Dispatcher, Controller) and demonstrate efficiency of VMDC(View, Model, Dispatcher, Controller) together. after demonstration this research present with next research.

• Nuclear Engineering and Technology
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• v.39 no.2
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• pp.133-142
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• 2007

The Electric Power Research Institute (EPRI) demonstrated a method for monitoring the performance of instrument channels in Topical Report (TR) 104965, 'On-Line Monitoring of Instrument Channel Performance.' This paper presents the results of several models originally developed by EPRI to monitor three nuclear plant sensor sets: Pressurizer Level, Reactor Protection System (RPS) Loop A, and Reactor Coolant System (RCS) Loop A Steam Generator (SG) Level. The sensor sets investigated include one redundant sensor model and two non-redundant sensor models. Each model employs an Auto-Associative Kernel Regression (AAKR) model architecture to predict correct sensor behavior. Performance of each of the developed models is evaluated using four metrics: accuracy, auto-sensitivity, cross-sensitivity, and newly developed Error Uncertainty Limit Monitoring (EULM) detectability. The uncertainty estimate for each model is also calculated through two methods: analytic formulas and Monte Carlo estimation. The uncertainty estimates are verified by calculating confidence interval coverages to assure that 95% of the measured data fall within the confidence intervals. The model performance evaluation identified the Pressurizer Level model as acceptable for on-line monitoring (OLM) implementation. The other two models, RPS Loop A and RCS Loop A SG Level, highlight two common problems that occur in model development and evaluation, namely faulty data and poor signal selection

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.350-353
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• 2013

In this paper, a hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is proposed. The designed phase calculator, which adopts redundant binary number systems and a pipelined architecture to improve throughput and speed, performs arctangent operation using vectoring mode of DCORDIC algorithm. Fixed-point MATLAB simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification, and the estimated performance is about 7.5 Gbps at 469 MHz clock frequency.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.1
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• International Journal of Advanced Culture Technology
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• v.9 no.1
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• pp.218-223
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• 2021

Pervasive enhancement and required enforcement of the Internet of Things (IoTs) in a distributed massively multiplayer online architecture have effected in massive growth of Big-Data in terms of server over-load. There have been some previous works to overcome the overloading of server works. However, there are lack of considered methods, which is commonly applicable. Therefore, we propose a combing Sparse Auto-Encoder and Load-Balancing, which is ProGReGA for Big-Data of server loads. In the process of Sparse Auto-Encoder, when it comes to selection of the feature-pattern, the less relevant feature-pattern could be eliminated from Big-Data. In relation to Load-Balancing, the alleviated degradation of ProGReGA can take advantage of the less redundant feature-pattern. That means the most relevant of Big-Data representation can work. In the performance evaluation, we can find that the proposed method have become more approachable and stable.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.4
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• pp.33-41
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• 2006

RSA cryptosystem is of great use in systems such as IC card, mobile system, WPKI, electronic cash, SET, SSL and so on. RSA is performed through modular exponentiation. It is well known that the Montgomery multiplier is efficient in general. The critical path delay of the Montgomery multiplier depends on an addition of three operands, the problem that is taken over carry-propagation makes big influence at an efficiency of Montgomery Multiplier. Recently, the use of the Carry Save Adder(CSA) which has no carry propagation has worked McIvor et al. proposed a couple of Montgomery multiplication for an ideal exponentiation, the one and the other are made of 3 steps and 2 steps of CSA respectively. The latter one is more efficient than the first one in terms of the time complexity. In this paper, for faster operation than the latter one we use binary signed-digit(SD) number system which has no carry-propagation. We propose a new redundant binary adder(RBA) that performs the addition between two binary SD numbers and apply to Montgomery multiplier. Instead of the binary SD addition rule using in existing RBAs, we propose a new addition rule. And, we construct and simulate to the proposed adder using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is faster by a minimum 12.46% in terms of the time complexity than McIvor's 2 method and existing RBAs.