• KSII Transactions on Internet and Information Systems (TIIS)
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• 제4권5호
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• pp.836-858
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• 2010

Web Services allow a user to integrate applications from different platforms and languages. Since mobile applications often run on heterogeneous platforms and conditions, Web Service becomes a popular solution for integrating with server applications. However, because of its verbosity, XML based SOAP messaging gives the possible overhead to the less powerful mobile devices. Based on the mobile client's behavior that it usually exchanges messages with Web Service continuously in a session, we design the Handheld Flexible Representation architecture. Our proposed architecture consists of three main components: optimizing message representation by using a data format language (Simple_DFDL), streaming communication channel to reduce latency and the Context-store to store context information of a session as well as redundant parts of the messages. In this paper, we focus on the Context-store and describe the architecture with the Context-store for improving the performance of mobile Web Service messaging. We verify our approach by conducting various evaluations and investigate the performance and scalability of the proposed architecture. The empirical results show that we save 40% of transit time between a client and a service by reducing the message size. In contrast to solutions for a single problem such as the compression or binarization, our architecture addresses the problem at a system level. Thus, by using the Context-store, we expect reliable recovery from the fault condition and enhancing interoperability as well as improving the messaging performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.85-88
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• 2000

Distributed Control System(DCS) is one of the best solutions to implement control systems because it provides continuous observation of control process and execution of commands to induce proper operations. In this paper, a design of control network for DCS in nuclear power plant is proposed. The proposed control network on DCS has a simple architecture and deterministic property. Thus, the proposed control network offers hard real-time periodic service. It also has redundant media for the fault-tolerance. As a result, high safety and reliability required in nuclear power plant are guaranteed.

• 정보처리학회논문지D
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• 제16D권6호
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• pp.881-888
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• 2009

본 연구에서는 소프트웨어 기반으로 물품관리를 하기 위한 VMDC(View, Model, Dispatcher, Controller) 아키텍처를 제안한다. 물품을 인력이 아닌 소프트웨어로 관리하기 위하여 여러 아키텍처들이 존재한다. MVC와 기존 아키텍처의 경우, 공통된 객체의 전달로 불필요한 데이터가 이동되는 문제점이 발생한다. 따라서 이와 같은 문제점을 해결하기 위하여 VMDC(View, Model, Dispatcher, Controller) 아키텍처를 제시하고자 한다. VMDC(View, Model, Dispatcher, Controller) 아키텍처의 Dispatcher(사령부)는 각 Controller(컨트롤러)가 필요로 하는 데이터를 파악하고 그것을 기반으로 하여 객체를 재구성함으로서 효율적인 데이터 이동을 하도록 한다. 또한 VMDC(View, Model, Dispatcher, Controller) 아키텍처를 이용하여 개발된 식품관리 프로그램으로 사용사례를 보이고, 효율성을 제시 후 향후 연구방향 또한 제시한다.

• Nuclear Engineering and Technology
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• 제39권2호
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• pp.133-142
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• 2007

The Electric Power Research Institute (EPRI) demonstrated a method for monitoring the performance of instrument channels in Topical Report (TR) 104965, 'On-Line Monitoring of Instrument Channel Performance.' This paper presents the results of several models originally developed by EPRI to monitor three nuclear plant sensor sets: Pressurizer Level, Reactor Protection System (RPS) Loop A, and Reactor Coolant System (RCS) Loop A Steam Generator (SG) Level. The sensor sets investigated include one redundant sensor model and two non-redundant sensor models. Each model employs an Auto-Associative Kernel Regression (AAKR) model architecture to predict correct sensor behavior. Performance of each of the developed models is evaluated using four metrics: accuracy, auto-sensitivity, cross-sensitivity, and newly developed Error Uncertainty Limit Monitoring (EULM) detectability. The uncertainty estimate for each model is also calculated through two methods: analytic formulas and Monte Carlo estimation. The uncertainty estimates are verified by calculating confidence interval coverages to assure that 95% of the measured data fall within the confidence intervals. The model performance evaluation identified the Pressurizer Level model as acceptable for on-line monitoring (OLM) implementation. The other two models, RPS Loop A and RCS Loop A SG Level, highlight two common problems that occur in model development and evaluation, namely faulty data and poor signal selection

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.350-353
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• 2013

본 논문에서는 TOF(Time-Of-Flight) 센서에 의해 얻어진 정보로부터 3차원 깊이 영상(depth image)을 추출하기 위한 위상 연산기의 하드웨어 구현을 제안한다. 설계된 위상 연산기는 DCORDIC(Differential COordinate Rotation DIgital Computer) 알고리듬의 vectoring mode를 이용하여 Arctangent 연산을 수행하며, 처리량과 속도를 늘리기 위해 redundant binary 수체계와 pipelined 구조를 적용하였다. 제안된 알고리듬은 고정 소수점 MATLAB 시뮬레이션을 통해 검증하고 최적 데이터 비트 수 및 반복 횟수를 결정하였다. 설계된 위상 연산기는 MATLAB/Simulink와 FPGA 연동을 통해 가상의 3차원 데이터 복원 동작을 검증하였으며, 469 MHz의 클록 주파수로 동작하여 7.5 Gbps의 성능을 갖는 것으로 평가되었다.

• 대한임베디드공학회논문지
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• 제12권1호
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• pp.11-18
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• 2017

Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• 센서학회지
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• 제24권3호
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.

• International Journal of Advanced Culture Technology
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• 제9권1호
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• pp.218-223
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• 2021

Pervasive enhancement and required enforcement of the Internet of Things (IoTs) in a distributed massively multiplayer online architecture have effected in massive growth of Big-Data in terms of server over-load. There have been some previous works to overcome the overloading of server works. However, there are lack of considered methods, which is commonly applicable. Therefore, we propose a combing Sparse Auto-Encoder and Load-Balancing, which is ProGReGA for Big-Data of server loads. In the process of Sparse Auto-Encoder, when it comes to selection of the feature-pattern, the less relevant feature-pattern could be eliminated from Big-Data. In relation to Load-Balancing, the alleviated degradation of ProGReGA can take advantage of the less redundant feature-pattern. That means the most relevant of Big-Data representation can work. In the performance evaluation, we can find that the proposed method have become more approachable and stable.

• 정보보호학회논문지
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• 제16권4호
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• pp.33-41
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• 2006

RSA 암호 시스템은 IC카드, 모바일 시스템 및 WPKI, 전자화폐, SET, SSL 시스템 등에 많이 사용된다. RSA는 모듈러 지수승 연산을 통하여 수행되며, Montgomery 곱셈기를 사용하는 것이 효율적이라고 알려져 있다. Montgomery 곱셈기에서 임계 경로 지연 시간(Critical Path Delay)은 세 피연산자의 덧셈에 의존하고 캐리 전파를 효율적으로 처리하는 문제는 Montgomery 곱셈기의 효율성에 큰 영향을 미친다. 최근 캐리 전파를 제거하는 방법으로 캐리 저장 덧셈기(Carry Save Adder, CSA)를 사용하는 연구가 계속 되고 있다. McIvor외 세 명은 지수승 연산에 최적인 CSA 3단계로 구성된 Montgomery 곱셈기와 CSA 2단계로 구성된 Montgomery 곱셈기를 제안했다. 시간 복잡도 측면에서 후자는 전자에 비해 효율적이다. 본 논문에서는 후자보다 빠른 연산을 수행하기 위해 캐리 전파 제거 특성을 가진 이진 부호 자리(Signed-Digit SD) 수 체계를 사용한다. 두 이진 SD 수의 덧셈을 수행하는 잉여 이진 덧셈기(Redundant Binary Adder, RBA)를 새로 제안하고 Montgomery 곱셈기에 적용한다. 기존의 RBA에서 사용하는 이진 SD 덧셈 규칙 대신 새로운 덧셈 규칙을 제안하고 삼성 STD130 $0.18{\mu}m$ 1.8V 표준 셀 라이브러리에서 지원하는 게이트들을 사용하여 설계하고 시뮬레이션 하였다. 그 결과 McIvor의 2 방법과 기존의 RBA보다 최소 12.46%의 속도 향상을 보였다.