• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.29-33
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• 2019

Recently, due to the rapid improvement of communication technologies as well as the easy production of video contents, IPTV is becoming increasingly popular. Meanwhile, as the number of IPTV channels increases rapidly, much time is required for finding the user's desired channel. This paper discusses and analyzes the effectiveness of reducing IPTV channel searching delays by using memory management techniques of computer systems. Specifically, this paper introduces how memory management techniques such as memory replacement, prefetching, and caching techniques can be adopted in IPTV channel searching interfaces by mapping between the two problems and discusses the effectiveness of the techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.1-7
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• 2006

This paper presents experimental instruction-level current consumption model for low power microcontroller ATmega128. The accessibility of instruction for internal memory decides power consumption of the microcontroller as much as 17% of difference between access instruction and non-access instruction. The power consumption for the given program will be increased in the proportional to the ratio of memory access instruction and lower level memory access in the hierarchy. Throughout the current consumption model, the power consumption can be predicted and optimized in the direction of reducing the frequency memory access. Also, the various optimization methods are introduced in terms of software and hardware viewpoints.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.439-446
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• 2001

The main stream of parallel programming today is using synchronous algorithms, where processor synchronization for correct computation and workload balance are essential. Overall performance of the whole system is dependent upon the performance of the slowest processor, if workload is not well-balanced or heterogeneous clusters are used. Asynchronous iteration is a way to mitigate such problems, but most of the works done so far are for shared memory systems. In this paper, we suggest and implement a parallel large sparse linear system solver that improves performance on distributed memory systems like clusters by reducing processor idle times as much as possible by asynchronous iterations.

• IEMEK Journal of Embedded Systems and Applications
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• v.17 no.4
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• pp.217-228
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• 2022

Currently, there are increasing demands for applying deep neural networks (DNNs) in the embedded domain such as classification and object detection. The DNN processing in embedded domain often requires custom hardware such as NPU for acceleration due to the constraints in power, performance, and area. Processing DNN models requires a large amount of data, and its seamless transfer to NPU is crucial for performance. In this paper, we developed a cycle-accurate NPU simulator to evaluate diverse NPU microarchitectures. In addition, we propose a novel technique for reducing the number of memory accesses when processing convolutional layers in convolutional neural networks (CNNs) on the NPU. The main idea is to reuse data with memory interleaving, which recycles the overlapping data between previous and current input windows. Data memory interleaving makes it possible to quickly read consecutive data in unaligned locations. We implemented the proposed technique to the cycle-accurate NPU simulator and measured the performance with LeNet-5, VGGNet-16, and ResNet-50. The experiment shows up to 2.08x speedup in processing one convolutional layer, compared to the baseline.

• The Korean Journal of Rehabilitation Nursing
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• v.1 no.1
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• pp.61-71
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• 1998

Defining prediction variables related to metamemory for the adults in aging process has worthwhile meaning from the perspective that the produced results can be helpful to reducing the difficulty of memorizing efforts and it can also enhance quality of life of aged. This study attempted to analysis relationship between perceived health status, depression, memory self-efficacy and meta memory for the subjects of middle age and old age adults. This study was designed by adopting descriptive correlational analysis method for the 468 middle and old age adults who are living in Seoul. Samples were selected by convenience sampling. Data collection was done over 1 month period in june 1998. The instruments used in this study were health status measuring scale including depression measuring scale, memory self efficacy measuring scale and metamemory measuring scale which were verified for reliability. Data collected were analized by using SPSS for frequency, Peason correlation, t-test and ANOVA according to the variables character and the study purposes. Results of the study were as follows. 1. Relationship between perceived health status, depression, memory self-efficacy and metamemory. Relational analyses between perceived health status, depression, memory self-efficacy and metamemory supported the hypotheses of 1st, 2nd and 3rd(p < .01). These results suggested that the aged perceived great health status then their memory self-efficacy, and metamemory showed the high scores. In the case of depression when its level became decreased metamemory was inclined to increased. Thus, it is identified that strong relationship exists between these variables. 2. Perceived health status, depression, memory self-efficacy by subject's general characteristics. Scores of perceived health status were high in the group of man compared to the group of women, and also highly educated group showed great perceived health status. Group of persons having occupation showed high score of perceived health status and low depression score. The score of memory self-efficacy and metamemory showed higher in the middle aged than the old aged. The high scores of memory self-efficacy and metamemory were found in the group of highly educated people and who have continuing education. The high scores of memory self-efficacy were found in the group of persons having their job and high metamemory scores found in the group of persons having religion. In summary, the greater perceived health status and memory self-efficacy, the more metamemory scores were likely increased and the more depression level was decreased, the more metamemory was likely increased. Also it was found that general characteristics like educational level, continuing education and religion influenced the metamemory of the aged. Therefore, prevention the aged from getting depression and activation of health promotion are needed to delay time of memory loss.

• Journal of KIISE:Software and Applications
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• v.37 no.9
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• pp.669-675
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• 2010

For detecting requirement errors in early system development phase, the behaviors of a system should be described in formal methods and be analyzed with analysis techniques such as reachability analysis and cycle detection. However, since they are usually based on explicit exploration of system state space, state explosion problem may be occurred when a system becomes complex. That is, the memory and execution time for exploration exponentially increase due to a huge state space. In this paper, we analyze the fundamental causes of this problem in concurrent systems and explore the state space without composing concurrent state spaces for reducing the memory requirement for exploration. Also our new technique keeps a visited history minimally for reducing execution time. Finally we represent experimental results which show the efficiency of our technique.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.989-997
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• 2018

Massive event stream brings us great challenges in its volume, velocity, variety, value and veracity. Picking up some valuable information from it often faces with long detection time, high memory consumption and low detection efficiency. Aiming to solve the problems above, an efficient complex event detection method based on NFA_HTS (Nondeterministic Finite Automaton_Hash Table Structure) is proposed in this paper. The achievement of this paper lies that we successfully use NFA_HTS to realize the detection of complex event from massive RFID event stream. Specially, in our scheme, after using NFA to capture the related RFID primitive events, we use HTS to store and process the large matched results, as a result, our scheme can effectively solve the problems above existed in current methods by reducing lots of search, storage and computation operations on the basis of taking advantage of the quick classification and storage technologies of hash table structure. The simulation results show that our proposed NFA_HTS scheme in this paper outperforms some general processing methods in reducing detection time, lowering memory consumption and improving event throughput.

• The KIPS Transactions:PartD
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• v.11D no.1
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• pp.11-22
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• 2004

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. Consequently, reducing cache misses emerges as the most important issue in current main memory databases, in which CPU speeds have been increasing at 60% per year, compared to the memory speeds at 10% per you. In this paper, we design and implement a main-memory database system for real-time mobile GIS. Our system is composed of 5 modules： the interface manager provides the interface for PDA users； the memory data manager controls spatial and non-spatial data in main-memory using virtual memory techniques； the query manager processes spatial and non-spatial query : the index manager manages the MR-tree index for spatial data and the T-tree index for non-spatial index : the GIS server interface provides the interface with disk-based GIS. The MR-tree proposed propagates node splits upward only if one of the internal nodes on the insertion path has empty space. Thus, the internal nodes of the MR-tree are almost 100% full. Our experimental study shows that the two-dimensional MR-tree performs search up to 2.4 times faster than the ordinary R-tree. To use virtual memory techniques, the memory data manager uses page tables for spatial data, non- spatial data, T-tree and MR-tree. And, it uses indirect addressing techniques for fast reloading from disk.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.125-134
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• 2004

Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.