• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.10A
• /
• pp.1590-1597
• /
• 2000

This paper describes a CMOS data recovery circuit using oversampling technique. Digital oversampling is done using a delay locked loop circuit locked to multiple clock periods. The delay locked loop circuit generates the vernier delay resolution less than the gate delay of the delay chain. The transition and non-transition counting algorithm for 4x oversampling was implemented for data recovery and verified through FPGA. The chip has been fabricated with 0.6um CMOS technology and measured results are presented.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10b
• /
• pp.1201-1204
• /
• 1996

The previous results on LTR methods for time delay systems need the solution of the operator-type Riccati equation. In addition, it can be difficult to make the target loop shape representing the design specification. This paper proposes a new LTR method for input-delayed systems using well-established LTR method for non-delay systems. For doing this, a time delay margin is derived and the time delay of the input-delayed systems is assumed less than equal to the time delay margin. A simple example is presented for illustrations.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.6 no.4
• /
• pp.1006-1025
• /
• 2012

Improving the quality of service in IP networks is a major challenge for real-time voice communications. In particular, packet arrival-delay variation, so-called "jitter," is one of the main factors that degrade the quality of voice in mobile devices with the voice-over Internet protocol (VoIP). To resolve this issue, a receiver-based enhanced timing recovery algorithm combined with active jitter estimation is proposed. The proposed algorithm copes with the effect of transmission jitter by expanding or compressing each packet according to the predicted network delay and variations. Additionally, the active network jitter estimation incorporates rapid detection of delay spikes and reacts to changes in network conditions. Extensive simulations have shown that the proposed algorithm delivers high voice quality by pursuing an optimal trade-off between average buffering delay and packet loss rate.

• Journal of Biomedical Engineering Research
• /
• v.29 no.1
• /
• pp.8-16
• /
• 2008

The aim of this study was to evaluate the motor recovery in 4 chronic hemiparetic patients with Fugl-Meyer (FM) and EMG characteristics before and after the training program. The training was performed at 1hr/day, 5days/week during 6 weeks in 4 chronic stroke patients. Electromyographic activities of the affected hand were recorded during isometric wrist flexion/ extension movements. In all patients, FM was significantly improved after the 6-week training. Onset/offset delay of muscle contraction significantly decreased in the affected wrist after the training. The co-contraction ratio of flexor/extensor muscles decreased significantly. Also, onset/offset delay of muscle contraction and co-contraction ratio correlates significantly with upper limb motor impairment and motor recovery. This EMG technique allows an objective evaluation of changes in muscle activity in post-stroke patients, providing easily measurable, quantitative indices of muscle characteristics.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.6
• /
• pp.629-636
• /
• 1988

The reduction of recovery time for delay, in the train movements, is generally realized through train operations in the shortest running time and it leads to maximum energy consumption. At the region of this shortest running time, the amount of energy consumption is sharply reduced according to the running time. So the effect for the energy savings can be largely obtained by furnishing a little spare time on train operations. In this paper, it has been modelized the delay and it's enlargement phenomena and formualted the relief patterns in order to restore the delay by restraint and relief of precedent traints. Also it has been proved the number of relief trains for minimum energy consumption exists and then represented one example of relief patterns.

• Journal of KIISE:Information Networking
• /
• v.31 no.2
• /
• pp.233-241
• /
• 2004

In this paper, we propose a packet-lossless fast rerouting scheme at a link/node fault in MPLS (Multiprotocol Label Switching) network with minimized accumulated buffer delay problem at ingress node. The proposed scheme uses a predefined, alternative LSP (Label Switched Path) In order to restore user traffic. We propose two restoration approaches. In the first approach, an alternative LSP is initially allocated with more bandwidth than the protected working LSP during the failure recovery phase. After the failure recovery, the excessively allocated bandwidth of the alternative LSP is readjusted to the bandwidth of the working LSP. In the second approach, we reduce the length of protected working LSP by using segment-based restoration. The proposed approaches have merits of (ⅰ) no buffer delay problem after failure recovery at ingress node, and (ⅱ) the smaller required buffer size at the ingress node than the previous approach.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.11
• /
• pp.5200-5222
• /
• 2017

The separation of control plane and data plane in Software Defined Network (SDN) makes it flexible to control the network behavior, while also causes some inconveniences to the link failure recovery due to the delay between fail point and the controller. To avoid delay and packet loss, pre-defined backup paths are used to reroute the disrupted flows when failure occurs. However, it may introduce large overhead to build and maintain these backup paths and is hard to dynamically construct backup paths according to the network status so as to avoid congestion during rerouting process. In order to realize congestion aware fast link failure recovery, this paper proposes a novel method which installs multi backup paths for every link via source routing and per-hop-tags and spread flows into different paths at fail point to avoid congestion. We carry out experiments and simulations to evaluate the performance of the method and the results demonstrate that our method can achieve congestion aware fast link failure recovery in SDN with a very low overhead.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.2
• /
• pp.324-328
• /
• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• Journal of Advanced Navigation Technology
• /
• v.7 no.2
• /
• pp.141-148
• /
• 2003

This paper presents and compares several techniques that detect the symbol rate of unknown received signal. Symbol rate is detected from the power spectral density of the circuits such as the delay and multiplier circuit, the square law circuit, and analytic signal, etc. As a result of discrete Fourier transform of the output signals of these circuits, a lot of spectral lines and some peaks appear in frequency domain and the position of first peak is corresponding to the symbol rate. If a spectral line on the frequency that is not located in symbol rate is larger than the first peak, the symbol rate is erroneously detected. Thus, the ratio between the value of first peak and the highest side spectral line is used for the measure of the performance of symbol rate detector. For the MPSK modulation, the analytic signal method shows better performance than the delay and multiplier and square law circuits when the received signal power is lager than -20dB. It is also noted that the delay and multiplier circuit is not able to detect the symbol rate for the QAM modulation.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.2 no.2
• /
• pp.82-102
• /
• 2008

Packet losses tend to occur during short error bursts separated by long periods of relatively error-free transmission. There is also a significant spatial correlation in loss among the receiver nodes in a multicast session. To recover packet transmission errors at the transport layer, tree-based protocols construct a logical tree for error recovery before data transmission is started. The current tree construction scheme does not scale well because it overloads the sender node. We propose a scalable recovery tree construction scheme considering these properties. Unlike the existing tree construction schemes, our scheme distributes some tasks normally handled by the sender node to specific nodes acting as repair node distributors. It also allows receiver nodes to adaptively re-select their repair node when they experience unacceptable error recovery delay. Simulation results show that our scheme constructs the logical tree with reduced message and time overhead. Our analysis also indicates that it provides fast error recovery, since it can reduce the number of additional retransmissions from its upstream repair nodes or sender node.