• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.531-532
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• 2006

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.261-273
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• 2016

Reconfigurable finite impulse response (FIR) filters whose filter coefficients and filter order change dynamically during run-time play an important role in the software defined radio (SDR) systems, multi-channel filters, and digital up/down converters. However, there are not many reports on such reconfigurable designs which can support dynamic variation of filter order and filter coefficients. The purpose of this paper is to provide an architectural solution for the FIR filters to support run-time variation of the filter order and filter coefficients. First, two straightforward designs, namely, (i) single-MAC based design and (ii) full-parallel design are presented. For large variation of the filter order, two designs based on (iii) folded structure and (iv) fast FIR algorithm are presented. Finally, we propose (v) high throughput design which provides significant advantage in terms of hardware and/or time complexities over the other designs. We compare complexities of all the five structures, and provide the synthesis results for verification.

• Journal of Information Processing Systems
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• v.7 no.1
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• pp.85-92
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• 2011

This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays ("mesh", for short). With additional O(n/m (n/m + log m)) time slowdown, it enables the mesh of size $m{\times}m$ with static row/column buses to simulate the mesh of the larger size $n{\times}n$ with reconfigurable row/column buses ($m{\leq}n$). This means that if a problem can be solved in O(T) time by the mesh of size $n{\times}n$ with reconfigurable buses, then the same problem can be solved in O(Tn/m (n/m + log m)) time on the mesh of a smaller size $m{\times}m$ without a reconfigurable function. This time-cost is optimal when the relation $n{\geq}m$ log m holds (e.g., m = $n^{1-\varepsilon}$ for $\varepsilon$ > 0).

• Korean Journal of Computational Design and Engineering
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• v.22 no.2
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• pp.129-140
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• 2017

This paper presents a systematic approach for design of timely and proper layouts of a manufacturing system facilitating reconfigurability, referred to as a reconfigurable manufacturing system. A proper methodology for design of a system layout is required for reconfiguration planning - adding or removing machines for supplying the exact capacity needed to fulfill market demands, as well as minimizing the cost of adding new machines. In this paper, theory of constraints is used to make reconfiguration manufacturing systems more cost-effective and efficiency. The proposed approach is validated by using a real industrial case. This paper suggests that the proposed study should be performed concurrently with the design of a new manufacturing system.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.418-429
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• 2018

This paper studies the decentralized position/force control problem for constrained reconfigurable manipulator without torque sensing. A novel joint torque estimation scheme that exploits the existing structural elasticity of the manipulator joint with harmonic drive model is applied for each joint module. Based on the estimated joint torque and dynamic output feedback technique, a decentralized position/force control strategy is presented. In order to solve the problem of controller parameter perturbation, the non-fragile robust technique is introduced into the dynamic output feedback controller. Subsequently, the stability of the closed-loop system is proved using the Lyapunov theory and linear matrix inequality (LMI) technique. Finally, two 2-DOF constrained reconfigurable manipulators with different configurations are applied to verify the effectiveness of the proposed control scheme in numerical simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.2
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• pp.63-70
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• 2019

To increase the efficiency of task on the desk, this paper proposes a reconfigurable desk. The proposed reconfigurable desk is based on the Pin Art technology. For the design of the proposed desk, the upper surface of the desk is divided into small units, and then the user easily controls the height of the divided pieces to make desk a desired shape by using the proposed user interface. The Arduino module controls the hardware and the user interface is configured by using Android applications, making it easy for anyone to use. Through extensive experiments, the proposed system shows that various types of deformations are possible and thus the utilization is very high by mounting diverse devices.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.87-92
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• 2018

One of the problems with the base station equipment is that there is a large difference between the replacement time of the hardware equipment such as the base station equipment and the radio access equipment, and the evolution period of the communication standard. Therefore, the base station communication platform must be flexible enough to handle the evolving communication standards after purchase. Recent research on reconfigurable communications platforms has focused on the efficient architecture of the communications platform to meet these requirements through software downloads while still using existing hardware. This paper presents a prototype of a base station communications platform based on the ETSI standard reconfigurable architecture. The communication platform presented in this paper is implemented as an ETSI standard reconfigurable architecture using a general-purpose DSP (Digital Signal Processor). In the implemented prototype, we verify the real-time feasibility of communication protocol updates through software reconfiguration.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2007.11a
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• pp.69-70
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• 2007

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.271-272
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• 2010