• Journal of Positioning, Navigation, and Timing
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• 제8권4호
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• pp.153-164
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• 2019

This paper presents the development of an end-to-end numerical simulator for signal design of the next generation global navigation satellite system (GNSS). The GNSS services are an essential element of modern human life, becoming a core part of national infra-structure. Several countries are developing or modernizing their own positioning and timing system as their demand, and South Korea is also planning to develop a Korean Positioning System (KPS) based on its own technology, with the aim of operation in 2034. The developed simulator consists of three main units such as a signal generator, a channel unit, and a receiver. The signal generator is constructed based on the actual navigation satellite payload model. For channels, a simple Gaussian channel and land mobile satellite (LMS) multipath channel environments are implemented. A software receiver approach based on a commercial GNSS receiver model is employed. Through the simulator proposed in this paper, it is possible to simulate the entire transceiver chain process from signal generation to receiver processing including channel effect. Finally, numerical simulation results for a simple example scenario is analyzed. The use of the numerical signal simulator in this paper will be ideally suited to design a new navigation signal for the upcoming KPS by reducing the research and development efforts, tremendously.

• 한국정보전자통신기술학회논문지
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• 제4권4호
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• pp.264-271
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• 2011

항공기의 계기착륙을 유도하는 시스템인 ILS(Instrument Landing System)는 1947년 ICAO(International Civil Aviation Organization)에서 국제표준으로 채택되어 현재는 상용시스템으로 출시되고 있다. 본 논문에서는 통합형 ILS 디지털 송수신 모듈의 설계방법을 제안하였다. 새롭게 제안한 것은 FPGA를 이용한 디지털 이중 AM 변복조기, 샘플링 클럭 생성을 위한 DDS(Direct Digital Synthesizer), DDC(Digital Down converter) 구조의 복조기, DSP 칩을 이용한 AM 스펙트럼 분석기의 디지털 설계 기법이다. 제안한 설계 방법의 유용성을 모듈 개발 및 실험을 통해 확인한 결과, 성능이 우수한 상용 시스템으로의 활용이 가능함을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.191-192
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• 2008

We give new definition of the effective-leakage and the signal to effective-leakage plus noise ratio (SELNR) to consider receiver combining motivated by the leakage. We propose a method to find jointly beamforming vector and combining vector for the two linear receivers (maximal ratio combining (MRC) receiver and minimum mean square error (MMSE) receiver) based on the SELNR.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.817-820
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• 1999

In this paper, we describes RF receiver module for IMT-2000 handset with 5MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier-, RF SAW filter, Down-converter, IF SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8㏈, 3㏈m at 2.14㎓, conversion gain of downconverter is l0㏈, dynamic range of AGC is 80㏈, and phase noise of PLL is -100 ㏈m, at 100KHz. The receiver sensitivity is -110㏈m, adjacent channel selectivity is -48㏈m.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2006년도 하계학술대회
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• pp.280-287
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• 2006

Advent of the new European satellite positioning system, Galileo will result in development of new satellite receivers such as, GPS/Galileo dual mode receiver. Furthermore, a new GNSS satellite receiver would be required to be self-reconfigured to certain navigational environments like, indoor, high interference, integrity, etc. In this paper, design and implementation issue of a FPGA based flexible GNSS receiver which gets navigation solution using L1 band signals of GPS and Galileo simultaneously is addressed.

• Journal of Electrical Engineering and information Science
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• 제3권2호
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• 한국자동차공학회논문집
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• 제4권6호
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• pp.187-195
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• 1996

Because an alternative refrigerant(HFC-134a) is being used instead of CFC-12 for automotive air-conditioning system, newly designed air-conditioning components are necessary due to changes in characteristics. Optimum design scheme for receiver dryer in an automotive air-conditioning system is described with emphases upon the volume of desiccant and container. The volume of the container, that is manufactured based on the study, is reduced down to one half of the existing receiver dryers.

• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• 전기전자학회논문지
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• 제14권4호
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• pp.283-290
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• 2010

본 연구는 광통신을 위한 10Gbps CMOS 수신기 회로 설계에 관한 것이다. 수신기는 포토다이오드, 트랜스임피던스 증폭기, 리미팅 증폭기, 등화기, 클락 및 데이터 복원 회로, 디멀티플렉서, 기타 입출력 회로 등으로 구성돼있다. 여러 광대역 혹은 고속 회로 기법을 써서 SONET OC-192 표준용 광통신에 적합한, 효과적이고 신뢰성 있는 수신기를 구현하고자 하였다.