• 제목/요약/키워드: receiver design

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디지털 레이더 수신기의 RF-수신단 설계 및 분석 (A Study on RF Receiver Design and Analysis of Digital Radar Receiver)

  • 임은재;황희근;이영철
    • 한국전자파학회논문지
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    • 제25권3호
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    • pp.282-288
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    • 2014
  • 본 논문에서는 디지털 레이더 수신기의 광대역 특성과 선형성을 확보하기 위해 동적 영역 파라미터를 중심으로 RF-수신단을 분석 및 설계하였다. 광대역 특성과 수신기의 동적 영역 개선을 위해 8.8~9.8 GHz의 광대역폭에서 저잡음 증폭기를 잡음원 매칭을 설계하여 잡음 지수를 최소화하였으며, 능동혼합기를 설계를 통한 수신기의 변환 이득 특성을 확보하여 RF-수신단의 선형성을 개선시켰다. 설계된 RF-수신단은 8.8~9.8 GHz의 광대역에서 이득 63 dB, 잡음 지수 1.2 dB을 얻었으며, RF-수신단의 동작영역은 75.8 dB의 특성을 나타내며, X-Band 디지털 레이더 수신기에 응용 가능함을 보였다.

저궤도 위성용 S-BAND 수신기 설계 및 제작 (Design and Fabrication of a S-BAND Receiver for Low Orbit Satellite)

  • 최영진
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.35-38
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    • 2005
  • In this study, S-Band receiver for low orbit satellite is implemented. The developed receiver is double super-heterodyne type and STDN compatible. Input/output frequency of receiver is 2034.747MHz and 18.414MHz used for KOMPSAT 2 satellite. Overall gain(@AGC=0V) and image rejection were 92.4dB and 50.2dB respectively. It was verified that receiver has stable performance to the temperature limit, power supply voltage variation and input signal level range.

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케스코드 증폭기와 인덕터 피킹기술을 이용한 광통신용 광 수신기의 설계 (Optical Receiver Design For Optical Communication Using Cascoded Amplifier with Inductor Peaking Technique)

  • 박정식;이강승;정윤하
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.305-308
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    • 1999
  • In this paper, a transimpedance optical receiver based on PIN/P-HEMT with cascoded input stage and inductor peaking technique was designed for several giga bits optical communication. Analysis of the receiver shows that cascoded input stage with inductor peaking increase bandwidth without sacrificing low frequence gain. The receiver achieved a low noise characteristic and maximally flat frequence response. It is shown that the 3-dB bandwidth of the designed receiver is 8.3 ㎓ and input equivalent noise current is as low as 16pA/√Hz to 10㎓.

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고속 디지털 MRI 모뎀 수신기 설계 (Design of Receiver in High-Speed digital Modem for High Resolution MRI)

  • 염승기;양문환;김대진;정관진;김용권;권영철;최윤기
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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    • pp.69-72
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    • 2000
  • This paper shows the more improved design of MRI receiver compared to conventional one based on Elscint Spectrometer. At first, the low-cost ADC is 16 bits, 3MHz sampling A/D converter Comparing to conventional one with signal bits of 14 bits, this device with those of 16 bits helps getting Improved the image resolution improved. If frequency is designed centering around 7.6 MHz to be satisfied in 10 MHz of maximum input bandwidth of ADC. For 1st demodulation, fixed IF is used for the purpose of the implementing multi nuclei system. Control parts & partial digital parts are integrated on one chip(FPGA). In DDC(Digital Down Converter), we got required bandwidth of LPF by controlling its decimation rate. With above considerations, we designed optimal receiver for high resolution imaging to be implemented through PC interface & experimental test of receiver of MRI after receiver's fabrication.

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$\mu\textrm$PD 7720을 이용한 32 채널용 MFC 디지털 수신기의 설계 및 구현 (Design and Implementation of 32CH. MFC Digital Receiver using uPD7720 Digital Signal processor)

  • 류근호;허욱열;홍갑일;홍현하
    • 대한전기학회논문지
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    • 제35권2호
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    • pp.47-54
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    • 1986
  • Hardware implementation of a 32-channel MFC digital receiver has not been easy and simple, because it requires real time processing of PCM data. In this paper, we introduce a method of designing an MFC digital receiver compactly by the channel distribution method. We have implemented the MFC digital receiver to process many cnannels by distributing channels of the TDM input data directly to the commercial digital signal processor chips(NEC uPD7720), and by carrying out the modified Goertzel Algorithm. The design of low cost, reliable, high speed, and compact MFC receiver will be shown.

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RF Receiver design for Satellite Digital Audio Reception (Antenna)

  • Kim, Jang-Wook;Jeon, Joo-Seong
    • 한국컴퓨터정보학회논문지
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    • 제24권7호
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    • pp.71-78
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    • 2019
  • This paper describes a design for a RF receiver to receive satellite digital audio service. The RF receiver designed in this study is a planar structure that is easy to install on the rooftop of a car and is compact in size. In addition, it can be applied to certain commercial models because it has low noise and high gain characteristics. The impedance bandwidth of antenna is 17.8%(415MHz), and the axial ratio is below 3dB as good properties for the bandwidth of 40MHz which is a satellite digital audio service band. Also, it had a broad radiation beamwidth of $95.41^{\circ}$ in H-plane and $117.45^{\circ}$ in E-plane. From the results of the field test of satellite digital audio service reception for the RF receiver, it demonstrated good C/N rate(10.2dB).

항공관제용 VHF대역 수신기 설계 및 구현에 관한 연구 (A Study on the Design and Realization of a VHF Receiver for Air Traffic Control)

  • 강석엽;박욱기;고민호;김용균;송병진;박효달
    • 한국항행학회논문지
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    • 제10권1호
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    • pp.26-33
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    • 2006
  • 본 논문에서는 항공관제용 VHF대역 무선 수신기 설계 및 제작에 관하여 연구하였다. 모든 회로는 블록 단위로 설계 제작하여 검증 후 최종적으로 통합하였으며, 크게 3개의 모듈 즉, 수신부, 제어부, 전원부로 구성하였다. 성능은 관제용 무선 수신기에 적합한 사양을 만족하도록 설계 제작하였으며, 특히 수신기에 있어서 가장 중요한 성능 지표인 수신 감도는 -113 dBm으로 기존 상용 제품 보다 우수하였다. 연구된 항공관제용 무선 수신기는 CNS/ATM의 기본 요소로 사용되기에 충분한 시스템이라고 판단된다.

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Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

  • Jung, Hyun-Yong;Youn, Jin-Sung;Choi, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권4호
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    • pp.443-450
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    • 2014
  • This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

실시간 정밀 GPS/GNSS를 위한 위성항법 수신기 망 구성 요소 설계 및 구현 (Design and Implementation of Receiver Network Elements for Real-Time Precise GPS/GNSS)

  • 김희성;이형근
    • 제어로봇시스템학회논문지
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    • 제16권2호
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    • pp.126-133
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    • 2010
  • Due to the deployment of various wireless networks originating from CDMA, GSM, and WLAN, it became very convenient to exchange information from one place to another. As compared with the traditional environments for one-way information distribution based on fixed radio frequency bands, the convenient wireless network environments will bring about many changes in positioning technologies based on global navigation satellites. Among the many changes to come, the reconfigurable receiver network is one of the most attractive concepts since it can be tailored to a specific application area among networked robots, formation flying, bridge monitoring, and traffic monitoring. As an initial study to develop a reconfigurable receiver network, this paper deals with the design and implementation of the key elements of the reconfigurable receiver netowork; server, broadcaster, and client. In the designed receiver network, a sever receives and decodes measurements from a reference receiver installed at a known location, a broadcaster processes and transfers the messages from servers to clients and manages connections with servers and clients, a client receives the messages from the broadcaster and performs differential positioning. A real-time experiment result is demonstrated to validate the functionalities of each network element.

W-CDMA RF 수신기 전단의 최소 요구사항 (Minimum Requirement of Front-End in W-CDMA RF Receiver)

  • 심재성;육종관;박한규;하동인
    • 한국전자파학회:학술대회논문집
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    • 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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    • pp.205-208
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    • 2002
  • This paper presents a quantitative analysis on the intermodulation product between transmitter W-CDMA leakage signal and receiver out of band blocker, and proposes design guide lines for overcoming the effect in receiver design. Our analysis shows that duplexer isolation, attenuation and LNA IIP3 are mainly responsible for the 3rd order intermodulation product. Analysis also shows that LNA IIP3 required for meeting 3GPP TS 34.121 specification is about 1 ㏈m with duplexer isolation of 50 ㏈ and duplexer attenuation of 24㏈.

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