• Journal of Positioning, Navigation, and Timing
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• v.8 no.4
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• pp.153-164
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• 2019

This paper presents the development of an end-to-end numerical simulator for signal design of the next generation global navigation satellite system (GNSS). The GNSS services are an essential element of modern human life, becoming a core part of national infra-structure. Several countries are developing or modernizing their own positioning and timing system as their demand, and South Korea is also planning to develop a Korean Positioning System (KPS) based on its own technology, with the aim of operation in 2034. The developed simulator consists of three main units such as a signal generator, a channel unit, and a receiver. The signal generator is constructed based on the actual navigation satellite payload model. For channels, a simple Gaussian channel and land mobile satellite (LMS) multipath channel environments are implemented. A software receiver approach based on a commercial GNSS receiver model is employed. Through the simulator proposed in this paper, it is possible to simulate the entire transceiver chain process from signal generation to receiver processing including channel effect. Finally, numerical simulation results for a simple example scenario is analyzed. The use of the numerical signal simulator in this paper will be ideally suited to design a new navigation signal for the upcoming KPS by reducing the research and development efforts, tremendously.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.264-271
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• 2011

ILS(Instrument Landing System) is the international standard system for approach and landing guidance. ILS was adopted by ICAO(International Civil Aviation Organization) in 1947 and is currently being used in commercial systems. To design the digital transmitter and receiver modules that can be mounted in the integrated ILS, we propose the digital design methods of digital double AM modulator and demodulator using FPGA chip, DDS(Direct Digital Synthesizer) for generation of sampling clock, demodulator of DDC(Digital Down Converter) structure, and spectrum analyzer using DSP chip. We demonstrate the efficiency of the proposed design method through experiments using developed transmitter and receiver modules. This system can be used as a high-performance commercial system.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.191-192
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• 2008

We give new definition of the effective-leakage and the signal to effective-leakage plus noise ratio (SELNR) to consider receiver combining motivated by the leakage. We propose a method to find jointly beamforming vector and combining vector for the two linear receivers (maximal ratio combining (MRC) receiver and minimum mean square error (MMSE) receiver) based on the SELNR.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.817-820
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• 1999

In this paper, we describes RF receiver module for IMT-2000 handset with 5MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier-, RF SAW filter, Down-converter, IF SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8㏈, 3㏈m at 2.14㎓, conversion gain of downconverter is l0㏈, dynamic range of AGC is 80㏈, and phase noise of PLL is -100 ㏈m, at 100KHz. The receiver sensitivity is -110㏈m, adjacent channel selectivity is -48㏈m.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.280-287
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• 2006

Advent of the new European satellite positioning system, Galileo will result in development of new satellite receivers such as, GPS/Galileo dual mode receiver. Furthermore, a new GNSS satellite receiver would be required to be self-reconfigured to certain navigational environments like, indoor, high interference, integrity, etc. In this paper, design and implementation issue of a FPGA based flexible GNSS receiver which gets navigation solution using L1 band signals of GPS and Galileo simultaneously is addressed.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• Transactions of the Korean Society of Automotive Engineers
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• v.4 no.6
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• pp.187-195
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• 1996

Because an alternative refrigerant(HFC-134a) is being used instead of CFC-12 for automotive air-conditioning system, newly designed air-conditioning components are necessary due to changes in characteristics. Optimum design scheme for receiver dryer in an automotive air-conditioning system is described with emphases upon the volume of desiccant and container. The volume of the container, that is manufactured based on the study, is reduced down to one half of the existing receiver dryers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• Journal of IKEEE
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• v.14 no.4
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• pp.283-290
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• 2010

This study is on the design of 10Gbps CMOS receiver circuits for fiber-optic communication. The receiver is made up of a photodiode, a transimpedance amplifier, a limiting amplifier, an equalizer, a clock and data recovery loop circuit, and a demultiplexer or demux with some auxiliary circuits including I/O circuits. Various wideband or high-speed circuit techniques are harnessed to realize a feasible, effective, and reliable receiver for a SONET fiber-optic standard, OC-192.