• Title/Summary/Keyword: receiver design

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Design & Implementation of Receiver RF Block for PCS Mobile Station (PCS 단말기의 수신단 고주파부 설계 및 구현)

  • 안상면;양운근
    • Proceedings of the IEEK Conference
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    • 2000.06a
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    • pp.65-68
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    • 2000
  • In this paper, design parameters are investigated and design procedure is established for PCS mobile station, especially for receiver RF block. And simulation environment to analyze parameters of the receiver RF block to determine whether it satisfies the receiver standard, IS-98C, is calculated. Design parameters are simulated and optimized. With simulated results, PCS mobile station is implemented and tested. Measured results show good agreement with simulation Design procedure can be used to get optimum characteristics for each of receiver block. By using optimum characteristics, mobile station can be designed more efficiently.

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System Level Design of Multi-standard Receiver Using Reconfigurable RF Block

  • Kim, Chang-Jae;Jang, Young-Kyun;Yoo, Hyung-Joun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.3
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    • pp.174-181
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    • 2004
  • In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

A study on the design of the transmitter-receiver of fuze sensor for discriminating target position (표적위치식별 신관센서 송수신장치 설계에 관한 연구)

  • 최재현
    • Journal of the Korea Institute of Military Science and Technology
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    • v.5 no.2
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    • pp.159-168
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    • 2002
  • In this paper, a study on the design of the transmitter-receiver of fuze sensor for discriminating target position is presented. We propose the algorithm for detecting target distance/direction through investigating the operational concept and principle of fuze sensor. Based on the algorithm, We design transmitter-receiver, calculate various design variables and estimate the performance of that one. The estimated result shows that the required performance of fuze sensor is satisfied. Further research on confirming the performance of proposed algorithm through encounter simulation test with real target and resolving problem will be continued.

Design of Optical Receiver with CDR using Delayed Data Topology (데이터 지연방식의 CDR을 이용한 광 송신기 설계)

  • Kim, Kyung-Min;Kang, Hyung-Won;Choi, Young-Wan
    • 한국정보통신설비학회:학술대회논문집
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    • 2005.08a
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    • pp.154-158
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    • 2005
  • In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.

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FPGA Implementation of Doppler Invarient Low Power BFSK Receiver Using CORDIC (CORDIC을 이용한 도플러 불변 저전력 BFSK 수신기의 FPGA구현)

  • Byon, Kun-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.8
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    • pp.1488-1494
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    • 2008
  • This paper is to design and implement a low power noncoherent BFSK receiver intended for future deep space communication using Xilinx System generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital design for better efficiency and reliability. The receiver functions on one bit data processing and supports main data rate 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT and multiplication of twiddle factor for low power is substituted by rotators. The design and simulation of the receiver is carried out in Simulink then the Simulink model is translated to the hardware model to implement FPGA using Xilinx System Generator and to verify performance.

Novel New Approach to Improve Noise Figure Using Combiner for Phase-Matched Receiver Module with Wideband Frequency of 6-18 GHz

  • Jeon, Yuseok;Bang, Sungil
    • Journal of electromagnetic engineering and science
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    • v.16 no.4
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    • pp.241-247
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    • 2016
  • This paper proposes the design and measurement of a 6-18 GHz front-end receiver module that has been combined into a one- channel output from a two-channel input for electronic warfare support measures (ESM) applications. This module includes a limiter, high-pass filter (HPF), power combiner, equalizer and amplifier. This paper focuses on the design aspects of reducing the noise figure (NF) and matching the phase and amplitude. The NF, linear equalizer, power divider, and HPF were considered in the design. A broadband receiver based on a combined configuration used to obtain low NF. We verify that our receiver module improves the noise figure by as much as 0.78 dB over measured data with a maximum of 5.54 dB over a 6-18 GHz bandwidth; the difference value of phase matching is within $7^{\circ}$ between ports.

Design of effective Receiver in Wireless Network using turbo code (무선망에서 Turbo 코드를 이용한 효율적 수신기 설계)

  • Seok, Gyeong-Hyu;Choi, Woo-Jin
    • The Journal of the Korea institute of electronic communication sciences
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    • v.7 no.5
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    • pp.975-981
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    • 2012
  • In this paper, we considered the received signal of the wideband CDMA systems using turbo code in the multipath channel environments, and analyze the performance of the system. This study is to analyze the performance for the variable system bandwidth according to the number of branches of rake receiver by passing the received signal through a rake receiver with a turbo code in Rayleigh fading channel environments. For the design of receiver in wideband CDMA systems, we presented the efficient parameters for the number of iterative decoding and the number of branches of rake receiver.

Design of Effective Receiver in Wideband-CDMA Systems Using Turbo Code

  • Cho, Seong-Chul
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.10
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    • pp.158-163
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    • 2006
  • In this paper, we considered the received signal of the wideband CDMA systems using turbo code in the multipath channel environments, and analyze the performance of the system. This study is to analyze the performance for the variable system bandwidth according to the number of branches of rake receiver by passing the received signal through a rake receiver with a turbo code in Rayleigh fading channel environments. For the design of receiver in wideband CDMA systems, we presented the efficient parameters for the number of iterative decoding and the number of branches of rake receiver.

Design and Implementation of the Small Size Microwave Sensor Receiver for Human Body Detection (인체 감지용 소형 마이크로파 센서 수신기의 설계 및 제작)

  • Son, Hong-Min;Choi, Hyun-Ho
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.4
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    • pp.403-406
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    • 2016
  • This paper presents the design and implementation of the small size receiver to put a passive microwave sensor for human body detection to practical use. The requirements and specifications of the sensor receiver are drawn using the experimental data of human body detection by the existing sensor operated at 5.1 GHz. The small size sensor receiver to satisfy the drawn specifications is designed and implemented. The effectiveness of the fabricated sensor with small size receiver on human body detection is demonstrated experimentally in laboratory. The results show the sensor can detect human body to within 4 m distance from the antenna. The size and power consumption of the small size receiver are decreased to 60 % and 40 % compared to those of the existing receiver, respectively.

Design of a PC based Real-Time Software GPS Receiver (PC기반 실시간 소프트웨어 GPS 수신기 설계)

  • Ko, Sun-Jun;Won, Jong-Hoon;Lee, Ja-Sung
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.55 no.6
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    • pp.286-295
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    • 2006
  • This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.