• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.416-419
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• 2015

In this paper, we propose an effective design of transform hardware for real-time HEVC(High Efficiency Video Coding) encoder. HEVC encoder determines the transform mode($4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$) by comparing RDCost. RDCost require a significant amount of computation and time because it is determined by bit-rate and distortion which is computated via transform, quantization, dequantization, and inverse transform. This paper therefore proposes a new method for transform mode determination using sum of transform coefficient. Also, proposed hardware architecture is implemented with multiplexer, recursive adder/subtracter, and shifter only to derive reduction of the computation. Proposed method for transform mode determination results in an increase of 0.096 in BD-PSNR, 0.057 in BD-Bitrate, and decrease of 9.3% in encoding time by comparing HM 10.0. The hardware which is proposed is implemented by 256K logic gates in TSMC 130nm process. Its maximum operation frequency is 200MHz. At 140MHz, the proposed hardware can support 4K Ultra HD video encoding at 60fps in real time.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.513-520
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• 2006

In this paper, we propose a novel real-time frame-layer rate control algorithm using sliding window method for low bit rate video coding. The proposed rate control method performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. A new frame-layer rate-distortion model is derived, and a non-iterative optimization method is used for low computational complexity. In order to reduce the quality fluctuation, we use a sliding window scheme which does not require the pre-analysis process. Therefore, the proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performance than the existing TMN8 rate control method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.7
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• pp.37-42
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• 2008

In this paper, a real-time multiview video coding system using fast disparity estimation is proposed. In the multiview encoder, adaptive disparity-motion estimation (DME) for an effective 3-dimensional (3D) processing are proposed. That is, by adaptively predicting the mutual correlation between stereo images in the key-frame using the proposed algorithm, the bandwidth of stereo input images can be compressed to the level of a conventional 2D image and a predicted image also can be effectively reconstructed using a reference image and adaptive disparity vectors. Also, in multiview decoder, intermediate view reconstruction (IVR) using adaptive disparity search algorithm (DSA) for real-time multiview video processing is proposed. The proposed IVR can reduce a processing time of disparity estimation by selecting adaptively disparity search range. Accordingly, the proposed multiview video coding system is able to increase the efficiency of the coding rate and improve the resolution.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.201-204
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• 2006

A system realization for real time DVR system with robust video watermarking algorithm against is attacked various is presented in this paper. The main system is composed of DSP processor and robust video watermarking to be processed at real time on image data and algorithm of the DVR system. The experimental result shows that the processing time takes about 2.5ms on the D1 size image per frame.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.6
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• pp.84-89
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• 2003

In this paper, we real-time implemented to the TMS320C5416 the vocoder of variable bit rate applied the SOLA-B algorithm by Henja to the ITU-T G.729A vocoder of 8kbps transmission rate. This proposed method using the SOLA-B algorithm is that it is reduced the duration of the speech in encoding and is played at the speed of normal by extending the duration of the speech in decoding. At this time, we bandied that the interval of cross correlation function if skipped every 3 sample for decreasing the computational amount of SOLA-B algorithm. The real-time implemented vocoder of C.729A and SOLA-B algorithm is represented the complexity of maximum that is 10.2MIPS in encoder and 2.8MIPS in decoder of 8kbps transmission rate. Also, it is represented the complexity of maximum that is 18.5MIPS in encoder and 13.1MIPS in decoder of 6kbps, it is 18.5MIPS in encoder and 13.1MIPS in decoder of 4kbps. The used memory is about program ROM 9.7kwords, table ROM 4.5kwords, RAM 5.1 kwords. The waveform of output is showed by the result of C simulator and Bit Exact. Also, for evaluation of speech quality of the vocoder of real-time implemented variable bit rate, it is estimated the MOS score of 3.69 in 4kbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5A
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• pp.545-553
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• 2004

Expansion of network environment and multimedia demand universality of application service as HDTV, etc. During these processes, it is essential to process multimedia in real time in the wireless communication system based on mobile phone network and in the wire communication system due to fiber cable and xDSL. So, in this Paper the optimal memory allocation algorithm combines the merit of huffman encoding which is superior in simultaneous decoding ability and lempel-ziv that is distinguished in execution of compress is proposed to improve the channel transmission rate and processing speed in the compressing procedure and is verified in the entropy encoder of HDTV. Because the entropy encoder system using proposed optimal memory allocation algorithm has memory saturation prevention we confirms that the compressing ratio for moving pictures is superior than Huffman encoding and LZW.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8B
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• pp.707-715
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• 2006

One of the most promising services on the wireless network is multimedia data service. With recently emerged wireless communication technologies which conventionally were devoted to mobile phone services, pre-encoded contents as well as live video data can be transmitted via the same network. As there is enough room in the improvement of data transmission bandwidth in wireless network, video data service is likely to be more demanding. In this paper, real time MPEG-4 video encoder is described as apart of a whole system for live video services over wireless networks. As there are minimal assumptions on the underlying networks, presented system and service can be easily supported by different network system.