• Transactions of the Korean Society of Automotive Engineers
• /
• v.6 no.4
• /
• pp.198-210
• /
• 1998

A crank angle-based engine control system has been developed for use as an engine research tool to provide precise control of the fuel injection(timing and duration) and ignition(timing and dwell) in real-time. The engine event information is provided by the engine shaft encoder, and the engine control system uses this information to generate spark and injector control signals for relevant cylinders. Eight different engine types and four different rotary encoder resolutions can be accommodated by this system. Also this system allows a user to individually control the ignition and fuel injection for each cylinder in a simple manner such as through a keyboard or in a real-time operation from a closed-loop control program.

• Journal of Broadcast Engineering
• /
• v.18 no.6
• /
• pp.835-849
• /
• 2013

Joint Collaborative Team on Video Coding (JCT-VC), which have founded ISO/IEC MPEG and ITU-T VCEG, has standardized High Efficiency Video Coding (HEVC). Standardization of HEVC has started with purpose of twice or more coding performance compared to H.264/AVC. However, flexible and hierarchical coding block and recursive coding structure are problems to overcome of HEVC standard. Many fast encoding algorithms for reducing computational complexity of HEVC encoder have been proposed. However, it is hard to implement a real-time HEVC encoder only with those fast encoding algorithms. In this paper, for implementation of software-based real-time HEVC encoder, data-level parallelism using SIMD instructions and CPU/GPU multi-threading methods are proposed. And we also proposed appropriate operations and functional modules to apply the proposed methods on HM 10.0 software. Evaluation of the proposed methods implemented on HM 10.0 software showed 20-30fps for $832{\times}480$ sequences and 5-10fps for $1920{\times}1080$ sequences, respectively.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.15 no.4
• /
• pp.44-48
• /
• 2006

Recently, demand the ultra precision product which is increasing rapidly is used extensively frontier industry field such as semi-conductor, computer, aerospace, precision machine. Ultra precision processing is the portion that is very needed to NT in the field of mechanical engineering. The latest date, together with radical advancement of electronic and photonics industry, necessity of ultra precision processing is on the increase for the manufacture of various kernel parts those are connected with these industrial fields. Specially, require motion accuracy of high resolution of nm order in stroke of hundreds millimeters according as diameter of processing object great and processing accuracy rises. In this case ,the response speed absolute delay because inertial mass of moving part is very large. Therefore, real time motion error compensation becomes very hardly. In this paper, we used ultra precision cutting unit(UPCU) to cope such problem. a UPCU is designed and tested to obtain sub-micrometer from accuracy in diamond turning of flat surfaces. The thermal growth spindle error is compensated for real time using a UPCU driven by piezoelectric actuator along with a laser encoder displacement sensor.

• ETRI Journal
• /
• v.32 no.4
• /
• pp.493-502
• /
• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• The KIPS Transactions:PartB
• /
• v.9B no.6
• /
• pp.715-726
• /
• 2002

In this paper, we construct real-time moving picture encoder based on fractal theory by using general purpose digital signal processors. The constructed encoder is implemented using two fixed-point general DSPs (ADSP2181) and performs image encoding by three stage pipeline structure. In the first pipeline stage, the image grabber acquires image data from NTSC standard image signals and stores digital image into frame memory. In the second stage, the main controller encode image dada using fractal algorithm. The last stage, output controller perform Huffman coding and result the coded data via RS422 port. The performance tests of the constructed encoder shows over 10 frames/sec encoding speed for QCIF data when all the frames are encoded. When we encode the images using the interframe and redundency based on the proposed algorithms, encoding speed increased over 30 frames/sec in average.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.5C
• /
• pp.371-381
• /
• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.565-568
• /
• 2005

Even though there has been a great deal of research and development for the compression techniques such as H.263, MPEG-1, and MPEG-2 in DVR systems, an efficient scheme for storing, accessing, and managing the huge amount of video data from multi-channel cameras needs to be developed. In this paper, we describe an implementation of MPEG-4 encoder for PC-based real-time multi-channel DVR systems.

• ETRI Journal
• /
• v.26 no.2
• /
• pp.122-135
• /
• 2004

Although frame-based MPEG-4 video services have been successfully deployed since 2000, MPEG-4 video coding is now facing great competition in becoming a dominant player in the market. Object-based coding is one of the key functionalities of MPEG-4 video coding. Real-time object-based video encoding is also important for multimedia broadcasting for the near future. Object-based video services using MPEG-4 have not yet made a successful debut due to several reasons. One of the critical problems is the coding complexity of object-based video coding over frame-based video coding. Since a video object is described with an arbitrary shape, the bitstream contains not only motion and texture data but also shape data. This has introduced additional complexity to the decoder side as well as to the encoder side. In this paper, we have analyzed the current MPEG-4 video encoding tools and proposed efficient coding technologies that reduce the complexity of the encoder. Using the proposed coding schemes, we have obtained a 56 percent reduction in shape-coding complexity over the MPEG-4 video reference software (Microsoft version, 2000 edition).

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.5
• /
• pp.849-855
• /
• 1987

This paper describes an implementation of the absolute moment block truncation coding(AMBTC) in real time for the moving picture data compression. We have realized a system composed of the encoder and decoder, and operated it using an NTSC TV signal. The encoder consists of a 4-1line buffer memory and a data processing block. Besides, there are signal conditioner and a control signal generator. Experimental results show that the quality of the processed image with a data rate of 10Mb/s is slightly degraded, but not objectionable, comparing data rate of 80Mb/s.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.400-402
• /
• 2007

This paper presents a vector control implementation for PMSM using Real Time Workshop and Embedded Target for TI C2000 DSP in MATLAB/SIMULINK. Speed, current and vector controllers are easily designed and implemented by using the MATLAB/SIMULINK program. Feedback of motor speed is processed through C28x QEP(Quadrature Encoder Pulse) block from encoder pulse. 3-Phase currents ares processed through C28x ADC block from current sensors. And gating signal of PWM inverter is generated through SVPWM and PWM block. Real-time program is drawn using SIMULINK and then converted program code for speed control of PMSM is downloaded into the TI eZdsp 2812 board. Experiments were carried out to examine validity of the proposed vector control implementation.