• 한국CDE학회논문집
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• 제19권3호
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• pp.294-304
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• 2014

This paper presents a real-time rendering algorithm of large-scale geometric data using GLSL (OpenGL shading language). It details the VAO (vertex array object) and VBO(vertex buffer object) to be used for up-loading the large-scale point clouds and polygon meshes to a graphic video memory, and describes the shader program composed by a vertex shader and a fragment shader, which manipulates those large-scale data to be rendered by GPU. In addition, we explain the global rendering procedure that creates and runs the shader program with the VAO and VBO. Finally, a rendering performance will be measured with application examples, from which it will be demonstrated that the proposed algorithm enables a real-time rendering of large amount of geometric data, almost impossible to carry out by previous techniques.

• 한국항행학회논문지
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• 제23권5호
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• pp.452-459
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• 2019

본 논문에서는 원격 측정 시스템 파라미터에 대한 실시간 업데이트가 가능한 PCM (pulse code modulation) 엔코더 구조에 대해 기술한다. PCM 엔코더 내부에는 FPGA (filed programmable gate array), flash 메모리, 센서 데이터 계측을 위한 아날로그 신호 조절부를 구성하였다. PCM 엔코더의 FPGA 내부에 로직을 통해 UART (universal asynchronous receiver/transmitter) 통신, 아날로그 신호 조절부 제어, flash 메모리 제어, 프레임 구성이 가능하다. UART 통신을 이용해 PC에서 파라미터 데이터를 PCM 엔코더에게 송신할 수 있으며, flash 메모리가 제어되어 원격 계측 시스템의 파라미터가 실시간으로 업데이트 되어 최종적으로 프레임이 구성된다. 시뮬레이션과 검증을 통해 파라미터 데이터의 실시간 업데이트 여부에 대해 확인하였으며, 제안된 구조를 이용하여 유연성과 편의성을 높인 원격 계측 시스템을 구성할 수 있음을 확인하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1767-1770
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• 2003

This paper proposes an efficient network architecture for reflective memory system (RMS). Using this architecture, the time for broadcasting a shared-data to all nodes can be significantly shortened. The device named topology conversion switch (TCS) is implemented to realize the network architecture. The implemented TCS is applied to the ethernet based real time control network (ERCnet) to evaluate the performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(4)
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• pp.119-122
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• 2000

Recently, many complex DSP (Digital Signal Processing) algorithms have being realized on RISC CPU due to good compilation, low power consumption and large memory space. But, real-time implementation of multiple DSP algorithms on RISC requires the minimum and efficient memory usage and the lower occupancy of CPU. In this thesis, the original floating-point code of MPEG-1 audio decoder is converted to the fixed-point code and then optimized to the efficient assembly code in time-consuming function in accord with RISC feature. Finally, compared with floating-point and fixed-point, about 30 and 3 times speed enhancements are achieved respectively. And 3~4 times memory spaces are spared.

• 한국통신학회논문지
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• 제14권5호
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• pp.561-570
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• 1989

본 논문에서는 Hopfield 신경회로망 모델에 기초한 bipolar 메모리 행렬을 광학적으로 실현하기 위해 수정된 모델에 대한 이론적 분석과 상용 LCTV를 이용한 Hopfield 연상메모리의 광학적 구현에 관하여 논하였다. 특히, 본 논문에서는 신경간의 연결인 메모리마스크를 처음으로 컴퓨터 그래픽과 연결된 LCTV 마스크를 사용하고 수정된 모델에서 시간에 따라 변하는 thresholding 값을 메모리 마스크에 한행을 추가해 광학적으로 얻을 수 있게 함으로서 Hopfield 모델에 기초한 광연산 메모리의 실시간 처리를 실현 하였다.

• 대한전자공학회논문지
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• 제27권6호
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• 보건의료산업학회지
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• 제7권2호
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• pp.179-190
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• 2013

This study evaluated the interest of parents of elementary school children on the examination with their memory of results, their consistency and their compliance with results sheets to improve effects of School dental health management project. This study recruited 1,334 second-, third-, fifth- and sixth-grade students at two elementary schools located in Daegu metropolitan city performing School Dental Examination Project in 2008 and investigated whether the students visited dental hospitals following results of the examination, how the parents remembered the results and how their memory was same with real results based on results of the examination, the parents' memory of results. The parents of second- and third-grade students showed good memory of malocclusion and number of Caries and higher consistency for dental caries. The parents of fifth- and sixth-grade students showed good memory of dental caries. Visiting rates of dental hospitals accordance with grade were 75.7% due to dental caries in second- and third-grade students and 60.5% due to malocclusion in fifth- and sixth-grade students. Among students with abnormal results of the examination, 77.1% of the children with dental caries of parents having same memory with real results visited the hospitals while 52.7% of those of parents having different memory with them did.

• 에너지공학
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• 제14권2호
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• pp.112-116
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• 2005

본 논문에서는 높은 대역폭과 안정성을 제공하는 DCS용 통신망의 구조를 제시하고 성능을 해석한다. 본 논문에서 제시하는 DCS용 통신망은 DCS 통신망에서 널리 사용되는 리플렉티브 메모리 (Reflective Memory) 구조를 채용하며, 이에 따라 링형 토폴로지를 가진다 물리계층으로 사무용 및 산업용으로 널리 쓰이고 있는 패스트 이더넷(Fast Ethernet)물리 매체를 사용하여 100 Mbps의 대역폭을 가지고, 링형 토폴로지가 가지는 단점인 각 노드에서의 시간 지연을 줄이기 위해 RED(Ring Enhancement Device)라는 장치를 고안하여 사용한다. 본 논문에서 소개하는 DCS용 통신망을 ERCNet(Ethernet based Real-time Control Network)이라고 명명하며, ERCNet의 구조와 동작에 대해 설명한다. ERCNet의 통신 성능에 대한 수학적 해석을 수행하고 개발된 ERCNet을 이용한 실험을 통하여 해석 결과의 정확성과 통신망 성능을 검증한다.

• 한국컴퓨터정보학회논문지
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• 제20권12호
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• pp.1-8
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• 2015

Wear leveling techniques have been studied to prolong the lifetime of NAND flash memory. Most of studies have used Program/Erase(P/E) cycles as wear index for wear leveling. Unfortunately, P/E cycles could not predict the real lifetime of NAND flash blocks. Therefore, these algorithms have the limited performance from prolonging the lifetime when applied to the SSD. In order to apply the real lifetime, wear leveling algorithms, which use raw Bit Error Rate(rBER) as wear index, have been studied in recent years. In this paper, we propose CrEWL(Cold data identification using raw Bit error rate in Wear Leveling), which uses rBER as wear index to apply to the real lifetime. The proposed wear leveling reduces an overhead of garbage collections by using HBSQ(Hot Block Sequence Queue) which identifies hot data. In order to reduce overhead of wear leveling, CrEWL does not perform wear leveling until rBER of the some blocks reaches a threshold value. We evaluate CrEWL in comparison with the previous studies under the traces having the different Hot/Cold rate, and the experimental results show that our wear leveling technique can reduce the overhead up to 41% and prolong the lifetime up to 72% compared with previous wear leveling techniques.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.257-258
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• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.