• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1094-1096
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• 1987

Zero-crossing analysis techniques have been applied to speech recognition. Zero-crossing rate, level-crossing rate and differentiated zero-crossing rate in time domain we used in analyzing speech signals. Speech samples could be stored in memory buffer in real time.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.347-351
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• 1991

We propose a real time kernel chimera implemented under AT&T UNIX motorola versoin, Carnegie Mellon Univ. in U.S first developed chimera using SUN Worstation with Berkley UNIX based on VMEbus. The major differences between Canegie Mellon's and ours are downloading program and communication method between host and target. Original chimera used device driver but we used UNIX system call corresponding to shared memory when user downloads program and communicates. We modified kernel itself because the two different UNIX have different link editor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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• pp.413-416
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• 2002

In this paper, a speech enhancement system using microphone array with adaptive Post-Processing is implemented in real-lime with TMS320C6201 DSP. It consists of delay-and-sum beamformer and adaptive post-processing filters with NLMS (Normalized Least Mean Square) algorithm. THS1206 ADC is used for collection of 4-channel microphone signals. Sizes of program memory, data ROM and data RAM of the implemented system are 15,744, 748 and 47,540 bytes, respectively. Finally 21.839${\times}$106 clocks per second is required for real-time operation.

• 인지과학
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• 제23권2호
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• pp.249-267
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• 2012

본 연구에서는 구문 처리에서 운율 정보 활용이 작업 기억 용량의 영향을 받는지를 검증하였다. 구체적으로 작업 기억 용량이 운율 경계의 강도와 위치에 따른 관계절 부착 중의성 해소 방식 차이를 예측하는지를 알아보았다. 실험 결과, 작업 기억 폭이 큰 청자들의 중의성 해소 방식이 작업 기억 폭이 작은 청자들에 비해 운율 경계 강도의 영향을 더 받는 것으로 나타났다. 이는 다른 상위 수준 제약과 마찬가지로 운율 제약의 활용도 작업 기억과 같은 인지적 자원을 필요로 함을 시사한다.

• 한국컴퓨터정보학회논문지
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• 제25권3호
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• pp.51-55
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• 2020

본 논문에서는 이미지 복원에 사용되는 기존의 FAM (Fuzzy Associative Memory)에 유사성 학습을 채택하여 개선된 FAM을 제안한다. 이미지 복원은 노이즈가 존재하는 버전에서 원 이미지에 가깝게 복원하는 것을 의미한다. 얼굴 인식과 같은 중요한 적용 문제에서 이 프로세스는 잡음에 강하고 견고하며 빠르며 확장 가능해야한다. 기존의 FAM 은 강력한 퍼지 제어를 통하여 도메인에 적용 할 수 있지만 실제 응용 프로그램에서는 용량 문제가 있지만 단순한 단일 계층 신경망이다. 유사성 측정은 복구 된 이미지와 원본 이미지 사이의 제곱 평균 오차를 최소화하기 위해 FAM 구조의 연결 강도와 관련이 있다. 제안된 알고리즘의 효과는 실험에서 랜덤 노이즈로 인한 오류 크기가 현저히 낮아지는 것을 확인하였다.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Structural Engineering and Mechanics
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• 제64권1호
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• pp.109-120
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• 2017

The behavior of moment resistant steel structures depends on both the beam-column connections and columns foundations connections. Obviously, if the connections can meet the adequate ductility and resistance against lateral loads, the seismic capacity of these structures will be linked practically to the performance of these connections. The shape memory alloys (SMAs) have been most recently used as a means of energy dissipation in buildings. The main approach adopted by researchers in the use of such alloys is firstly bracing, and secondly connecting the beams to columns. Additionally, the behavior of these alloys is modeled in software applications rarely involving equivalent torsional springs and column-foundation connections. This paper attempts to introduce the shape memory alloys and their applications in steel structural connections, proposing a new steel column-foundation connection, not merely a theoretical model but practically a realistic and applicable model in structures. Moreover, it entails the same functionality as macro modeling software based on real behavior, which can use different materials to establish a connection between the columns and foundations. In this paper, the suggested steel column-foundation connection was introduced. Moreover, exploring the seismic dynamic behavior under cyclic loading protocols and the famous earthquake records with different materials such as steel and interconnection equipment by superelastic shape memory alloys have been investigated. Then, the results were compared to demonstrate that such connections are ideal against the seismic behavior and energy dissipation.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2006년도 Proceedings of ISRS 2006 PORSEC Volume II
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• pp.725-727
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• 2006

The development of GIS and Location-Based Services requires a high-level database that will be able to allow real-time access to moving objects for spatial and temporal operations. MODB.MM is able to meet these requirements quite adequately, providing operations with the abilities of acquiring, storing, and querying large-scale moving objects. It enables a dynamic and diverse query mechanism, including searches by region, trajectory, and temporal location of a large number of moving objects that may change their locations with time variation. Furthermore, MODB.MM is designed to allow for performance upon main memory and the system supports the migration on out-of-date data from main memory to disk. We define the particular query for truncation of moving objects data and design two migration methods so as to operate the main memory moving objects database system and file-based location storage system with.

• 한국전자통신학회논문지
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• 제15권3호
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• pp.457-464
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• 2020

한국군은 Link-11, Link-16 과 Link-K를 적용한 한국형 전술 데이터링크 체계 JTDLS(: Joint Tactical Data Link System)를 운용하고 있다. Link-11에서 Link-22로의 교체 시점이 도래함에 따라 JTDLS 완성형 사업에서는 기존의 전술 데이터링크 외에 Link-22 등의 전술 데이터링크 처리가 추가될 예정이다. 다양한 전술 데이터링크 메시지 처리를 위해 본 논문에서는 Link-K, Link-16, KVMF 등 다중 전술 데이터링크의 데이터를 처리 할 수 있는 데이터 관리 구조를 제안하고, DLP 측면에서 많은 데이터를 빠르게 처리하는 방안을 찾기 위한 Shared Memory, In-Memory DB, 자체개발 DB를 이용하여 모의시험을 진행하고, 그 결과를 확인해 보고자 한다.

• Journal of Communications and Networks
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• 제17권3호
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• pp.286-295
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• 2015

Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.