• Journal of IKEEE
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• v.18 no.3
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• pp.403-408
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• 2014

In this paper, we propose a rasterizer architecture using varying interpolator which process several pixels at a time. Proposed rasterizer is able to handle 16 pixel at a time and output the color of up to 64. It can reduce the redundancy of calculation by configuring a matrix transformation and matrix calculation for rasterization, and it can enhance the speed of rasterizer by increasing the reusability. As a result, proposed rasterizer has improve 11% in color interpolation, 17% in the processing speed of the rasterizer by comparing with conventional research.

• Journal of IKEEE
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• v.21 no.3
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• pp.276-279
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• 2017

In this paper, SIMT structure based GPGPU (General Purpose Computing on Graphics Processing Units) is used for accelerating the Rasterizer which constitutes the screen of the display device in pixel unit. The GPU has a large number of ALUs, and the processing is very fast because of parallel processing. Therefore, in this paper, we implemented a rasterizer that generates a 3D graphics model using a CPU that performs operations sequentially and a GPU that performs operations in parallel. We confirmed that proposed rasterizer in this paper is 1.45 times better than rasterizer using Intel CPU when generating one frame.

• Journal of IKEEE
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• v.16 no.4
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• pp.304-309
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• 2012

As resolution for displays is recently more and more increasing, the amount of data abd calculation that graphic hardware needs to process are also increasing. Especially the amount of data processing by rasterizer is rapidly increasing. This paper used an algorism using coordinates in center of gravity and area for triangle instead of using bilinear algorism[1] used by conventional interpolation, which is to make it easier for parallel processing by rasterizer. This paper implemented designed rasterizer under FPGA environment, and compared it with conventional rasterizer and verified it. This rasterizer is proved to have approximately 50% higher performance compared to conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.89-96
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• 2007

In this paper, we designed 3D graphics rasterizer with a culling and clipping for the efficient 3D graphics accelerator. The proposed rasterizer is implemented for the mobile system and process frustum culling, back face culling, Y-axis clipping and X-axis clipping. The rasterzier consists of triangle setup, edge walk and span process unit. Each unit of rasterzier is designed with a culling and clipping. It supports goraud shading with 16 bits depth values and 16 bits color values. The estimated performance of proposed rasterizer is 52M pixels per second.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.85-86
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• 2001

3D parallel rasterizer on a single chip for high performance generates consistency problem. To solve this problem, 3D parallel rasterizer with consistency buffer Os proposed. This can simultaneously process a plurality of Primitives. Experimental results show 1.1-2.0x speedups using a simple model. This method can achieve high performance and cost effectiveness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.309-311
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• 2014

The tile-based rendering technique which divides the screen area into tiles of a specific size and creates a 3D graphic model of one tile at a time is used to efficiently utilize limited resources in a 3D graphic pipeline. In this paper, the tiling speed of tile-based rendering was improved by reducing the count of calling lower-levels in the hierarchical tile-based rendering technique. The tiling speed of the proposed Rasterizer is 13.030ms which is 56% faster than 29.614ms of multi-sort tiling and 24% faster than 17.208ms of the conventional hierarchical tiling technique.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.639-642
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• 2009

When the graphics accelerator for high-quality multimedia content design, hardware verification environment, easy and accurate performance evaluation in an embedded device is required. To work around this is not verified through the simulation waveform analysis to determine the actual calculated graphic images has designed a software rasterizer. Rasterizer is designed for Windows-based environment using the C language implementation of rasterization has a function at each step. Vertex data is entered and the results were verified.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.221-224
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• 2009

본 논문에서는 OpenVG Specification에서 제안한 파이프라인을 기능별, 혹은 연산별로 그룹화 하여 하드웨어 구현에 적합한 새로운 파이프라인을 제안하였다. 래스터라이저에서는 스캔라인 알고리즘과 엣지 플래그 알고리즘의 장점들을 포함하는 스캔라인 엣지 플래그 알고리즘을 구현하여 적용하였으며, Non-Zero 룰을 만족하기 위해 엣지의 방향에 따라 Winding 횟수를 기록하기 위한 추가 버퍼를 이용하였다. 또한, 래스터라이저는 안티 앨리어싱을 위해 슈퍼 샘플링 과정을 수행한다. 액티브 엣지 생성 시 클리핑을 동시에 수행하여 이후 과정에서의 불필요한 연산을 줄였고, 액티브 엣지들의 정렬을 수행하지 않는 방법을 사용하여 처리 속도를 향상 시켰다. 본 연구에서 설계된 OpenVG Rasterizer는 크로노스 그룹에서 제공하는 샘플 이미지들을 사용하여 검증하였다.

• Journal of IKEEE
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• v.19 no.4
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• pp.590-595
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• 2015

This paper proposes a design of efficient hierarchy structure in the tile based rasterizer. The proposed hierarchy structure avoids unnecessary calls of low level tile at which a calculation is not required. A low level tile is classified into three categories based on its maximum, minimum position, and inside outside test. The necessity of calculations on the corresponding low level tile can be determined by its classification. The overall amount of computations for graphic processing can be reduced by not calling for the low level tile with no calculation. The proposed hierarchy structure can reduce an execution time of graphic processing. It shows higher efficiency with the more vertex density of formulating 3D model.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.11 no.6
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• pp.58-64
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• 1993