• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.08a
• /
• pp.186-186
• /
• 2010

소자의 축소화에 따라 floating gate 형의 flash 메모리 소자는 얇은 게이트 절연막 등의 이유로, 이웃 셀 간의 커플링 및 게이트 누설 전류와 같은 문제점을 지니고 있다. 이러한 문제점을 극복하기 위해 charge trap flash 메모리 (CTF) 소자가 연구되고 있지만, CTF 메모리 소자는 쓰기/지우기 속도와 데이터 보존 성능간의 trade-off 관계와 같은 문제점을 지니고 있다. 최근, 이를 극복하기 위한 방안으로, 다른 유전율을 갖는 유전체들을 적층시킨 터널 절연막을 이용한 Tunnel Barrier Engineered (TBE) 기술이 주목 받고 있다. 따라서, 본 논문에서는 TBE 기술을 적용한 MIS-capacitor를 높은 유전율을 가지는 Al2O3와 HfO2를 이용하여 제작하였다. 이를 위해 먼저 Si 기판 위에 Al2O3 /HfO2 /Al2O3 (AHA)를 Atomic Layer Deposition (ALD) 방법으로 약 2/1/3 nm의 두께를 가지도록 증착 하였고, Aluminum을 150 nm 증착 하여 게이트 전극으로 이용하였다. Capacitance-Voltage와 Current-Voltage 특성을 측정, 분석함으로써, AHA 구조를 가지는 터널 절연막의 전기적인 특성을 확인 하였다. 또한, high-k 물질을 이용한 터널 절연막을 급속 열처리 공정 (Rapid Thermal Annealing-RTA) 과 H2/N2분위기에서 후속열처리 공정 (Post-RTA)을 통하여 전기적인 특성을 개선 시켰다. 적층된 터널 절연막은 열처리를 통해 터널링 전류의 민감도의 향상과 함께 누설전류가 감소됨으로서 우수한 전기적인 특성이 나타남을 확인하였으며, 적층된 터널 절연막 구조와 적절한 열처리를 이용하여 빠른 쓰기/지우기 속도와 전기적인 특성이 향상된 비휘발성 메모리 소자를 기대할 수 있다.

• Electrical & Electronic Materials
• /
• v.10 no.8
• /
• pp.800-806
• /
• 1997

The behavior of de levels in rapid thermal annealed Fe-doped semi-insulating InP(100) was studied by photoinduced current transient spectrocopy(PICTS). In bulk InP, T2(Ec-0.24 eV), T3(Ec-0.30 eV) and T5(Ec-0.62 eV) traps were observed. After annealing the T2 trap was annihilated at 20$0^{\circ}C$ and recreated at 35$0^{\circ}C$. T3 trap was not affected below 40$0^{\circ}C$. With increasing temperature the concentration of T5 trap reduced and it was annihilated at 30$0^{\circ}C$. However the T1(Ec-0.16 eV) and T4(Ec-0.42 eV) traps were began to appear at 40$0^{\circ}C$and these concentrations were increased with annealing temperature. The T1 and T4 traps seem to be related to the isolated phosphorus vacancy( $V_{p}$) and $V_{p}$-indium antisite( $V_{p}$- $P_{in}$ ) or $V_{p}$-indium interstitial( $V_{p}$-I $n_{I}$) respectiely.respectiely.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.25-26
• /
• 2008

Electrical properties of Pt/Ti/Au/Pt contacts to n-GaAs were characterized as the V/III ratio of GaAs grown by metalorganic chemical vapor deposition were 25, 50, and 100, respectively. The samples have been annealed during 30sec at 350 and $450^{\circ}C$ in rapid thermal annealing, and those specific contact resistance investigated by using transmission line method. According to experimental results, the specific contact resistance between p-metal and GaAs was decreased as the V/III ratio was lower. These results indicate that Si doping concentration of GaAs increased as the vacancy of V-series of GaAs was high.

• Proceedings of the KSME Conference
• /
• 2004.04a
• /
• pp.1370-1375
• /
• 2004

This article investigates the heat transfer characteristics in a RTA system for LCD manufacturing and suggests a way to evaluate the quality of a poly-Si film from the thin film optics analysis. The transient and one-dimensional conductive/radiative heat transfer equation considering wave interference effect is solved to predict surface temperatures of thin films. In dealing with radiative heat transfer, a one-dimensional two-flux method is used and the ray tracing method is also utilized to account for the wave interference effects. It is assumed that each interface is assumed diffusive but the spectral radiative properties are included. It is found that the selective heating region exists for various wavelengths and consequently may contribute to heat the poly-Si film. Using the formalism of the characteristic transmission matrix, the lumped structure reflectance, transmittance, and absorptance are calculated and they are compared with experimental data of the poly-Si film during the SPC process via the FE-RTA (Field-Enhanced RTA) technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.1
• /
• pp.11-16
• /
• 2016

The conduction behavior and electron concentration change in a-IGZO thin-films according to the RTA (rapid thermal annealing) were studied. The electrical characteristics of TFTs (thin-film-transistors) annealed by different temperatures were measured. The sheet resistance, electron concentration, and oxygen vacancy of a-IGZO film were measured by the four-point-probe-measurement, hall-effect-measurement, and XPS analysis. The RTA process increased the driving current of IGZO TFTs but the VTH shifted to the negative direction at the same time. When the RTA temperature is higher than $250^{\circ}C$, the leakage current at off-state increased significantly. This is attributed to the increase of oxygen vacancy resulting in the increase of electron concentration. We demonstrate that the RTA is a promising process to adjust the VTH of TFT because the RTA process can easily modify the electron concentration and control the conductivity of IGZO film with short process time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1997.11a
• /
• pp.21-24
• /
• 1997

Ferroeletric LiNbO$_3$ thin films hale been prepared directly on Si(100) substrates by conventional RF magnetron spurttering system for nonvolatile memory applications. As-deposited films were performed RTA(Rapid Thermal Annealing) treatment in an oxygen atmosphere at 600 $^{\circ}C$ for 60 s. The rapid thermal annealed films were changed to poly-crystalline ferroelectric nature from amorphous of as-deposition. The resistivity of the ferroelectric LiNbO$_3$ film was increased from a typical vague of 1~2$\times$10$^{8}$ $\Omega$.cm before the annealing to about 1$\times$10$^{13}$ $\Omega$.cm at 500 kV/cm and reduce the interface state density of the LiNbO$_3$/Si(100) interface to about 1$\times$10$^{11}$ cm$^2$ . eV. Ferroelectric hysteresis measurements using a Sawyer-Tower circuit yielded remanent polarization (Pr) and coercive field (Ec) values of about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively.

• Journal of the Korean Ceramic Society
• /
• v.27 no.2
• /
• pp.249-255
• /
• 1990

High Tc Supperconducting thin films were fabricated by rf magnetron sputtering method. We have successfully controlled the compositions of films by adding sintered CuO pellets on YBa2Cu3O7-x single target. High Tc thin films with large grian size and good crystal habit were obtained by rapid thermal annealing process. The films deposited on SrTiO3(100) single crystal substrate indicated the existence of c-axis prefered orientation confirmed by XRD and SEM analysis. The Tc, zero's of sharp resistive transition for rapid annealed films deposited on polycrystalline YSZ substrate and on SrTiO3(100) single crystal substrate were 79K and 88K, respectively.

• Korean Journal of Materials Research
• /
• v.11 no.9
• /
• pp.776-780
• /
• 2001

$SiO_2$ and polycrystalline Si layers were sequentially grown on (100) Si. NiSi was formed on this substrate from a 20nm Ni layer or a 20nm Ni/5nm Ti bilayer by rapid thermal annealing (RTA) at $300~500^{\circ}C$ to compare thermal stability. In addition, MOS capacitors were fabricated by depositing a 20nm Ni layer on the Poly-Si/$SiO_2$substrate, RTA at $400^{\circ}C$ to form NiSi, $BF_2$ or As implantation and finally drive- in annealing at $500~800^{\circ}C$ to evaluate electrical characteristics. When annealed at $400^{\circ}C$, NiSi made from both a Ni monolayer and a Ni/Ti bilayer showed excellent thermal stability. But NiSi made from a Ni/Ti bilayer was thermally unstable at $500^{\circ}C$. This was attributed to the formation of insignificantly small amount of NiSi due to suppressed Ni diffusion through the Ti layer. PMOS and NMOS capacitors made by using a Ni monolayer and the SADS(silicide as a dopant source) method showed good C-V characteristics, when drive-in annealed at $500^{\circ}C$ for 20sec., and$ 600^{\circ}C$ for 80sec. respectively.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.416-419
• /
• 2008

In this study, we report on the characteristics of Aldoped ZnO (AZO) co-sputtered indium tin oxide (ITO) films prepared by dual target direct current (DC) magnetron sputtering at room temperature for organic light emitting diodes (OLEDs). The electrical and optical properties of co-sputtered IAZTO electrode were critically dependent on the DC power of AZO. Furthermore, the characteristics of co-sputtered IAZTO electrode were influenced by rapid thermal annealing temperature.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.1
• /
• pp.31-36
• /
• 2002

Low energy boron ions were implanted into the preamorphized and crystalline silicon substrates to form 0.2${\mu}m$ $p^+-n$ junctions. The rapid thermal annealing(RTA) was used to annihilate the crystal defects due to implantation and to activate the implanted boron ions, and the furnace annealing was employed to reflow the BPSG(bolo-phosphosilicate glass). The implantation conditions for Gepreamorphization were the energy of 45keV and the dose of 3$\times$1014cm-2. BF2 ions employed as a p-type dopant were implanted with the energy of 20keV and the dose of 2$\times$1015cm-2. The thermal conditions of RTA and furnace annealing were $1000^{\circ}C$/10sec and $850^{\circ}C$/40min, respectively. The junction depths were measured by SIMS and ASR techniques, and the 4-point probe was used to measure the sheet resistances. The electrical characteristics were analyzed via the leakage currents of the fabricated diodes. The single thermal processing with RTA produced shallow junctions of good qualities, and the thermal treatment sequence of furnace anneal and RTA yielded better junction characteristics than that of RTA and furnace anneal.