• Korean Journal of Materials Research
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• v.14 no.7
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• pp.477-481
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• 2004

High quality polycrystalline silicon is very critical part of the high quality thin film transistor(TFT) for display devices. Metal induced lateral crystallization(MILC) is one of the most successful technologies to crystallize the amorphous silicon at low temperature(below $550^{\circ}C$) and uses conventional and large glass substrate. In this study, we observed that the MILC behavior changed with abrupt variation of the amorphous silicon active pattern width. We explained these phenomena with the novel MILC mechanism model. The 10 nm thick Ni layers were deposited on the glass substrate having various amorphous silicon patterns. Then, we annealed the sample at $550^{\circ}C$ with rapid thermal annealing(RTA) apparatus and measured the crystallized length by optical microscope. When MILC progress from narrow-width-area(the width was $w_2$) to wide-width-area(the width was $w_1$), the MILC rate decreased dramatically and was not changed for several hours(incubation time). Also the incubation time increased as the ratio, $w_1/w_2$, get larger. We can explain these phenomena with the tensile stress that was caused by volume shrinkage due to the phase transformation from amorphous silicon to crystalline silicon.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.32-35
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• 2013

In this paper, a manufacturing process was developed for fabricating high-quality AlGaN/GaN high electron mobility transistors (HEMTs) on silicon carbide (SiC) substrates. Various conditions and processing methods regarding the ohmic contact and pre-metal-deposition $BCl_3$ etching processes were evaluated in terms of the device performance. In order to obtain a good ohmic contact performance, we tested a Ti/Al/Ta/Au ohmic contact metallization scheme under different rapid thermal annealing (RTA) temperature and time. A $BCl_3$-based reactive-ion etching (RIE) method was performed before the ohmic metallization, since this approach was shown to produce a better ohmic contact compared to the as-fabricated HEMTs. A HEMT with a 0.5 ${\mu}m$ gate length was fabricated using this novel manufacturing process, which exhibits a maximum drain current density of 720 mA/mm and a peak transconductance of 235 mS/mm. The X-band output power density was 6.4 W/mm with a 53% power added efficiency (PAE).

• Journal of Sensor Science and Technology
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• v.17 no.4
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• pp.250-255
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• 2008

A vanadium pentoxide ($V_2O_5$)-based bolometric infrared (IR) sensor has been designed and fabricated using micro electro mechanical systems (MEMS) technology for glucose detection and its resistive characteristics has been illustrated. The proposed bolometric infrared sensor is composed of the vanadium pentoxide array that shows superior temperature coefficient of resistance (TCR) and standard silicon micromachining compatibility. In order to achieve the best performance, deposited $V_2O_5$ thin film is optimized by adequate rapid thermal annealing (RTA) process. Annealed vanadium oxide thin film has demonstrated a linear characteristic and relatively high TCR value (${-4}%/^{\circ}C$). The resistance of vanadium oxide is changed by IR intensity based on glucose concentration.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.500-500
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• 2013

특정한 유기 물질에 전류를 인가했을 때 발광을 하는 특성을 이용한 Organic Light Emitting Diode (OLED)는 뛰어난 색재현성, 적은 전력소모, 간단한 제조공정, 넓은 시야각 등으로 인해 PDP, LCD, LED에 이은 차세대 디스플레이 소자로 많은 관심을 받고 있다. 하지만 OLED는 각기 다른 굴절률을 가지는 다층구조로 되어있어 실질적으로 소자 밖으로 나오는 빛은 원래 생성된 빛의 20% 정도 밖에 되지 않는다. 이러한 광 손실을 줄이기 위해 Photonic Crystal (PC)이나 마이크로 렌즈 어레이(MLA) 부착 등과 같이 특정한 크기를 갖는 주기적인 나노 구조물을 이용한 광추출 효율 상승 방법은 특정 파장의 빛에서만 효과가 있는 한계가 있었으며 고가의 공정과정을 거쳐야 했으므로 OLED 소자의 가격 향상에 일조하였다. 이의 해결을 위해 본 연구는 유리기판 위에 랜덤한 분포를 가지는 나노 구조물 제작 공정법을 제안한다. 먼저 유리기판 위에 스퍼터로 금속 박막을 입혀 이를 Rapid thermal annealing (RTA) 공정을 이용하여 랜덤한 분포의 Island를 가지는 마스크를 제작하였다. 그 후 플라즈마 식각을 이용하여 유리기판에 나노 구조물을 형성하였고 기판 위에 남아있는 마스크는 Ultrasonic cleaning을 이용하여 제거하였다. 제작된나노구조물은 200~300 nm의 높이와 약 200 nm 폭을 가지고 있다. 제작된 유리기판의 OLED 소자로의 적용가능성을 알아보기 위한 광학특성 조사결과는 300~900 nm의 파장영역에서 맨유리와 거의 비슷한 수직 투과율을 보이면서 최대 50%정도의 Diffusion 비율을 나타내고 있고 임계각(41도) 이상의각도에서 인가된 빛의 투과율에 대해서도 향상된 결과를 보여주고 있다. 제안된 공정의 전체과정 기존의 PC, MLA 등의 공정에 비해 난이도가 쉽고 저가로 진행이 가능하며 추후 OLED 소자에 적용될 시 대량생산에 적합한 후보로 보고 있다.

• Korean Journal of Materials Research
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• v.17 no.6
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• pp.323-330
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• 2007

We fabricated thermaly evaporated 10 nmNi/(poly)Si films to investigate the energy saving property of silicides formed by rapid thermal annealing (RTA) at the temperature of $300{\sim}1200^{\circ}C$ for 40 seconds. Moreover, we fabricated $10{\sim}50$ nm-thick ITO/Si films with a rf-sputter as reference films. A four-point tester was used to investigate the sheet resistance. A transmission electron microscope (TEM) and an X-ray diffractometer were used for the determination of cross sectional microstructure and phase changes. A UV-VISNIR and FT-IR (Fourier transform infrared rays spectroscopy) were employed for near-IR and middle-IR absorbance. Through TEM analysis, we confirmed $20{\sim}70nm-thick$ silicide layers formed on the single and polycrystalline silicon substrates. Nickel silicides and ITO films on the single silicon substrates showed almost similar absorbance in near-IR region, while nickel silicides on polycrystalline silicon substrate showed superior absorbance above 850 nm near-IR region to ITO films. Nickel silicide on polycrystalline substrate also showed better absorbance in middle IR region than ITO. Our result implies that nano-thick nickel silicides may have exellent absorbing capacity in near-IR and middle-IR region.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.454-461
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• 2015

Light enhancement of GaN based light emitting diodes (LEDs) have been investigated by texturing the top p-GaN surface. Nano-textured LEDs have been fabricated using self-assembled Ni nano mask during dry etching process. Experimental results were further compared with simulation data. Three types of LEDs were fabricated: Conventional (planar LED), Surface nano-porous (porous LED) and Surface nano-cluster (cluster LED). Compared to planar LED there were about 100% and 54% enhancement of light output power for porous and cluster LED respectively at an injection current of 20 mA. Moreover, simulation result showed consistency with experimental result. The increased probability of light scattering at the nano-textured GaN-air interface is the major reason for increasing the light extraction efficiency.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.45-51
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• 2001

The effects of wettability and surface oxidation on the low temperature and ultra-fine solder bump formation have been studied. Difference sequences of near eutectic In-Ag and eutectic Bi-Sn solders were evaporated on Au/Cu/Cr or Au/Ni/Ti Under Bump Metallurgy (UBM) pads. Solder bumps were formed using lift-off method and were reflowed in Rapid Thermal Annealing (RTA) system. The solder bumps in which In was in contact with UBM in In-Ag solder and the solder bumps in which Sn was in contact with UBM in Bi-Sn solder showed better bump formability during reflow than other solder bumps. The ability to form spherical solder bumps was affected mainly by the wettability of solders to UBM pads.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.234-239
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• 2007

This paper describes the TiW ohmic contact characteristics under the surface treatment of the polycrystalline 3C-SiC thin film grown on $SiO_2/Si(100)$ wafers by APCVD. The poly 3C-SiC surface was polished by using CMP(chemical mechanical polishing) process and then oxidized by wet-oxidation process, and finally removed SiC oxide layers. A TiW thin film as a metalization process was deposited on the surface treated poly 3C-SiC layer and was annealed through a RTA(rapid thermal annealing) process. TiW/poly 3C-SiC was investigated to get mechanical, physical, and electrical characteristics using SEM, XRD, XPS, AFM, optical microscope, I-V characteristic, and four-point probe, respectively. Contact resistivity of the surface treated 3C-SiC was measured as the lowest $1.2{\times}10^{-5}{\Omega}cm^2$ at $900^{\circ}C$ for 45 sec. Therefore, the surface treatments of poly 3C-SiC are necessary to get better contact resistance for extreme environment MEMS applications.