• 한국재료학회지
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• 제5권1호
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• pp.42-54
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• 1995

$Ta_2O_5$박막은 고유전율의 특성으로 차세대 DRAM캐패시터 물질로 유망받고 있는 물질이다. 본 연구에서는 p-type(100)Si 웨이퍼 위에 열 MOCVD 방법으로 $Ta_2O_5$박막을 성장시켰으며 기판온도, 버블러 온도, 반응압력의 조업조건이 미치는 영향을 고찰하엿다. 증착된 박막은 SEM, XRD, XPS, FT-IR, AES, TEM, AFM을 이용하여 분석하였으며 질소나 산소 분위기의 furnace 열처리 (FA)와 RTA(Rapid Thermal Annealing)를 통하여 열처리 효과를 살펴보았다. 반응온도에 따른 증착속도는 300 ~ $400 ^{\circ}C$ 범위에서 18.46kcal/mol의 활성화 에너지를 가지는 표면반응 율속단계와 400 ~ $450^{\circ}C$ 범위에서 1.9kcal/mol의 활성화 에너지를 가지는 물질전단 율속단계로 구분되었다. 버블러 온도는 $140^{\circ}C$일때 최대의 증착속도를 보였다. 반응압력에 따른 증착속도는 3torr에서 최대의 증착속도를 보였으나 굴절율은 0.1-1torr사이에 $Ta_2O_5$의 bulk값과 비슷한 2.1정도의 양호한 값이 얻어졌다. $400^{\circ}C$에서 층덮힘은 85.71%로 매우 양호하게 나타났으며 몬테카를로법에 의한 전산모사 결과와의 비교에 의해서 부착계수는 0.06으로 나타났다. FT-IR, AES, TEM 분석결과에 의하여 Si와 $Ta_2O_5$ 박막 계면의 산화막 두께는 FA-$O_{2}$ > RTA-$O_{2}$ ~ FA-$N_{2}$ > RTA-$N_{2}$ 순으로 성장하였다. 하지만 질소분위기에서 열처리한 박막은 산소분위기의 열처리경우에 비해 박막내의 산소성분의 부족으로 인한 그레인 사이의 결함이 많이 관찰되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 한국전기전자재료학회논문지
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• 제12권1호
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• pp.62-68
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• 1999

Ferroelectric $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$(x=0, 0.1, 0.2, 0.3) thin films were deposited on $Pt/SiO_2/Si$ substrate by MOD(Metalorganic Decomposition) process. Metal carboxylate and metal alkoxide were used as precursors, and 2-methoxyethanol, xylene as solvents. After spin coating, thin films were pre-annealed at $400^{\circ}C$, followed by RTA(Rapid Thermal Annealing) and final annealing at $800^{\circ}C$ in oxygen atmosphere. These procedures were repeated three times to obtain thin films with the thickness of $2000{\AA}$. To enhance the nucleation and growth of layered-perovskite phase, thin films were rapid-thermally annealed above $720^{\circ}C$ in oxygen atmosphere. As RTA temperature increased, fluorite phase was transformed to layered-perovskite phase. And the change of Nb contents affected dielectric / electrical properties and microstructure. The ferroelectric characteristics of $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$ thin film were Pr=8.67 $\mu{C}/cm^2$, Ec=62.4kV/cm and $I_{L}=1.4\times10^{-7}A/cm^2$ at the applied voltage of 5V, respectively.

• 한국재료학회지
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• 제12권11호
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• 대한전자공학회논문지
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• 제27권1호
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• pp.81-90
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• 1990

In this study, ion beam deposited tungsten thin film for gate material of GaAs SAGFET(Self Aligned Gate FET) was annealed from 800\ulcorner to 900\ulcorner using RTA and detailed investigations of structural and electrical characteristics of this film were carried out using four-point probe, XRD, SEM, AES and current-voltage measurement. Investigated results showed phase of as deposited tungsten film was fine grain \ulcornerphase and phase tdransformation of this film into \ulcornerphase occured at annealing condition of 900\ulcorner, 6sec. But regardless of phase transformation, electrical characteristics of tungsten film were very stable to 900\ulcorner and in case of 900\ulcorner, 4sec annealing condition Schottky barrier height obtained from 10 diodes measurements was 0.66 + 0.003 eV.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1477-1479
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• 2000

The annealing treatments on rf magnetron sputtered PZT($Pb_{1.05}(Zr_{0.52},Ti_{0.48})O_3$) thin films(4000${\AA}$) have been investigated for a structure of PZT/Pt/Ti/ITO coated glass. Crystallization properties of PZT films were strongly dependent on RTA(Rapid Thermal Annealing) annealing temperature and time. We were able to obtain a perovskite structure of PZT at 650$^{\circ}C$ and 10min. P-E curves of Pd/PZT/Pt capacitor demonstrate typical hysteresis loops. The measured values of $P_r$, $E_c$ were 15.8[${\mu}C/cm^2$], 95[kV/cm] respectively. Polarization value decrease about 10% after $10^9$ cycles.

• 한국재료학회지
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• 제2권3호
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• pp.213-219
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• 1992

$As^{+}$이온을 주입시킨후 열처리 방법을 달리한 Si 표면부 미세구조와 성분분석 및 전기적특성을 조사하였다. 이온주입에 의해 형성되었던 비정질층은 열처리에 의해 결정화 되었으며 열처리방법에 따라 결정화 양상의 차이를 보였다. 또한 주입된 이온의 분포 및 전기저항을 미세구조와 비교한 결과 주입된 이온의 농도가 최대인 깊이에서 최대의 손상이 발견되었으며 열처리 후에도 매우 작은 결함이 존재하였다. 하지만 이러한 작은 결함들은 전기적 성질에 큰 영향을 미치지는 않은 것으로 나타났다.

• 한국전기전자재료학회논문지
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• 제11권3호
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• pp.237-241
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• 1998

In this study, PLZT stock solutions around x/65/35 (x=6~11) ferroelectric region were prepared by Sol-Gel method and deposited on ITO-glass by spin-coating method. The thin films were annealed by RTA(rapid thermal annealing). The variations of crystallographic structure of the thin films were observed using XRD and hysteresis curves, dielectric characteristics, and optical transmittances were measured in order to investigate the characteristics of the thin films. The thin films were crystallized at $750^{\circ}C$ for 5 min by RTA. Relative dielectric constant and optical transmittance increased with increasing La content, Ec and Pr were higher for thin films than for bulk materials.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.139-142
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• 2002

Characteristics of piezoelectric thick films prepared by screen printing were investigated. The piezoelectric thick films were fabricated using Pb(Al,Nb)O$_3$-Pb(Zr,Ti)O$_3$ system on Si-substrate. The fabricated thick films were burned out at 400$^{\circ}C$ and sintered at 850∼1000$^{\circ}C$ using rapid thermal annealing(RTA) precess. The thickness of piezoelectric thick films were 10$\mu\textrm{m}$. PAN-PZT thick film on Ag-Pd/SiO$_2$/Si prepared at 900$^{\circ}C$/1300sec had remanent polarization of 19.70 ${\mu}$C/$\textrm{cm}^2$.

• 대한전자공학회논문지
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• 제25권6호
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• pp.647-653
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• 1988

A rapid thermal annealing system using tungsten halogen lamp has been designed and assembled. A control scheme where the temperature control is executed with calculated wafer temperature by considering the thermocouple delay rather than measured thermocouple temperature,is proposed. This control scheme gives more accurate control of the wafer temperature. In addition, the distribution of transmitted light power to the wafer in the system has been simulated, and lamp interval modification has been able to give more uniform light power distribution. Considering incident light spectrum, absorption, reflection, radiation of silicon, etc., temperature profile has been simulated. When the light power uniformity on the 3" wafer is below 1%, the temperature uniformity is about 2%.