• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.591-600
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• 2010

In this paper, three kinds of 24 GHz low-power CMOS cross-coupled voltage controlled oscillators are designed and fabricated for a short-range radar applications using TSMC 0.13 ${\mu}m$ CMOS process. The basic CMOS crosscoupled voltage controlled oscillator is designed for oscillating around a center frequency of 24.1 GHz and subthreshold oscillators are developed for low power operation from it. A double resonant circuit is newly applied to the subthreshold oscillator to improve the problem that parasitic capacitance of large transistors in a subthreshold oscillator can push the oscillation frequency toward lower frequencies. The fabricated chips show the phase noise of -101~-103.5 dBc/Hz at 1 MHz offset, the output power of -11.85~-15.33 dBm and the frequency tuning range of 475~852 MHz. In terms of power consumption, the basic oscillator consumes 5.6 mW, while the subthreshold oscillator does 3.3 mW. The subthreshold oscillator with the double resonant circuit shows relatively lower power consumption and improved phase noise performance while maintaining a comparable frequency tuning range. The subthreshold oscillator with double resonances has FOM of -185.2 dBc based on 1 mW DC power reference, which is an about 3 dB improved result compared with the basic oscillator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.376-383
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• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each subsystem, this partition will cause unwanted effects. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is used for the way of maintaining radiated emission, still specific user's guide doesn't give sufficient principle. In a view point of EMI, design principle of multi-CB using method will be analyzed by measurement. And design principle of noise mitigation will be provided. Generally interval of multi-CB is ${\lambda}/20$ ferrite bead. In this study, When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of EMI.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.366-375
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• 2008

Generally a return current plane(RCP) of high speed digital and analog part is partitioned. This is achieved in order to decrease the noise interference between subsystem in PCBs(Printed Circuit Boards). However, when the connected signal line exists between each sub system, this partition will cause unwanted effects. In a circuital point of view, RCP partition has a bad influence upon signal integrity. In a EMI(Electromagnetic Interference) point of view, the partition of the return current plane becomes a primary factor to increase the radiated emission. Component bridge(CB) is usecl for the way of maintaining signal integrity, still specific user's guide doesn't give sufficient principle. In a view point of signal integrity, design principle of multi-CB using method will be analyzed by measurement and simulation. And design principle of noise mitigation will be provided. Generally interval of CB is ${\lambda}/20$ ferrite bead. In this study. When multi-CB connection is applied, design principle of ferrite bead and chip resistor is proved by measurement and simulation. Multi-connected chip resistance$(0{\Omega})$ is proved to be more effective design method in the point of signal integrity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of Advanced Marine Engineering and Technology
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• v.38 no.6
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• pp.730-736
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• 2014

Test standards for electrical and electronic equipment required for ship operations is applying the IEC-60533 standard. However, although a test procedure and a specified regulation are clearly defined in the deck and bridge zone and general power distribution zone, they are not regulated in the special power distribution zone with ship propulsion system. For these reasons, the costs for additional research and development have been invested. In this paper, we was measured power noise in a special power distribution zone in ship and we were compared and analyzed values measured. The actual experiments are performed on the ship of Korea Maritime and Ocean University. As a result, the acquired data on Hanbada shows that loop antenna with low frequency band(160kHz) and ultra log antenna with high frequency band(1.97GHz)occur about 6-8dB differences and about 8.7 difference respectively. Also, the acquired data on Hannara shows that each loop antenna of 1MHz, 11MHz, and 25MHz occurs about 7dB difference about 4-5dB differences respectively. so standard of Special distribution zone must be specified by comparative analysis of data obtained by the experiment more.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.333-340
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• 2011

KJJVC(Korea-Japan Joint VLBI Correlator) was installed at the KJCC(Korea-Japan Correlation Center) and has been operated by KASI(Korea Astronomy and Space Science Institute) from 2009. KJNC is able to correlate the VLBI observed data through KVN(Korean VLBI Network), VERA(VLBI Exploration of Radio Astrometry), and JVN(Japanese VLBI Network) and its joint network array. And it is used exclusively as computer in order to process the observed data for the scientific purpose KJJVC used the VSI(VLBI Standard Interface) as the VLBI international standard at the data input-output specification between each component. Especially, for correlating the observed data, the data is transmitted with 1024Mbps speed between Mark5B high-speed playback and RVDB(Raw VLBI Data Buffer). The EMI(Electromagnetic lnterference), which is occurred by data transmission with high-speed, cause the data loss and the loss occurrence is frequently often for long transmission cable. Finally it will be caused the data recognition error by decreasing the voltage level of digital data signal. In this paper, in order to minimize the data loss by measuring the EMI noise level in transmission of the VSI specification, the 3 methods such as 1) RC filtering method, 2) lmpedance matching using Microstrip line, and 3) Signal buffering method using Differential line driver, were proposed. To verify the effectiveness of each proposed method, the performance evaluation was conducted by implementing and simulations for each method. Each proposed method was effectively confirmed as the high-speed data transmission of the VSI specification.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.23-36
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• 2005

PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.389-398
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• 2011

In this paper, the design and fabrication of a transmit/receive(T/R) module for Ka-band phased array radar is presented. A 5bit digital phase shifter and digital attenuator were used in common for both transmitter and receiver considering unique Ka-band characteristic. The circulator was excluded in the T/R module and was placed outside T/R module. The transmitting power per element antenna is designed to be about 1 W and the noise figure is designed to be below 8 dB. The designed T/R module RF part has a compact size of $5\;mm{\times}4\;mm{\times}57\;mm$. In order to implement the T/R module, MMICs used in T/R module was separately assessed before assembly of the designed T/R module. The transmitter of the fabricated T/R module shows about 1 W at 5 dBm unit module input power and the receiver shows a gain of about 20 dB and a noise figure of below 8 dB as expected in the design stage.