• KIEE International Transactions on Electrophysics and Applications
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• 제3C권6호
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• pp.220-223
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• 2003

In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.112-115
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• 2007

A CMOS TDC(time-to-digital converter) is proposed which has a simple cyclic structure. The proposed TDC consists of pulse-shrinking elements, D latches and D flip-flops. The operation is based on pulse-shrinking of the input pulse. The resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements, D latches and D flip flops. The TDC performance is improved in viewpoints of power consumption and chip area. Simulation results are shown to illustrate the performance of the proposed TDC circuit.