• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1212-1213
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• 2011

PWM(pulse width modulation) rectifier has unit power factor and low harmonic distortion with high power conversion efficiency in entire loading range. These merits of PWM rectifier help the spread of DC distribution system. In addition, if multiple PWM rectifiers can be operated in parallel connection, maintenance process can be simple and reliability of power source can be advanced because of the hot swapping is available. The other way, the load unbalance among rectifiers can force a converter to stop by over current. The surge current by closed circuit composition between rectifiers can force switching devices damage. In this paper, some problems that can occur in case of parallel operation of PWM rectifiers and problem eliminating methods are considered.

• Journal of Power Electronics
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• 제9권6호
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• pp.866-873
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• 2009

In general, the output voltage level of a PV array varies widely at various irradiances and temperatures. The MPP (Maximum Power Point) range of a medium- or high-power PV PCS is normally 450~830Vdc or 300~600Vdc. This means the PV PCS should operate in a wide range of modulation indexes. The PV PCS should satisfy the harmonic current requirement that the TDD (Total demand distortion) shall not exceed 5%. This paper proposes a new PWM control method for a medium- or high-power PV PCS which increases the efficiency of power conversion in all operation ranges with acceptable harmonic ripple currents. This paper compares and analyzes appropriate PWM schemes for the PV PCS in the view points of conversion efficiency and current harmonics.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.1088-1091
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• 1992

Programmed PWM(Pulse Width Modulated) generation techniques eliminating several low order harmonics have been widely used in the inverter circuit which produces minimum current ripple, reduced torque pulsation and thereby improves overall system performance. However, the applications of the programmed PWM technique are limited to CVCF(Constant Voltage Constant Frequency) applications and various motor drives. Although the programmed PWM produces a lower harmonic distorted waveform than the carrier modulated PWM, real-time programming is not possible because of the complicated calculation required for the gating signal. In this paper, a new programmed PWM technique named TAM (time averaging model) is developed to compensate for the demerits of the conventional programmed PWM technique with moderate harmonic distortion. Computer simulations are performed to verify the performance of the proposed algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.1104-1107
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• 1992

Voltage controlled current regulated PWM(pulse width modulation) of VSI (voltage source inverter) is proposed. Adopting one degree of freedom, the voltage, the current controller shows much more improvement than conventional ones not using this method. The voltage controller or this proposal needs load's parameters, torque value, rotational speed. This voltage controller is located at converter part which links AC source and DC bus. With this proposed method, duty ratio of the inverter's switching is nearly unity for all speed and torque range. Hence, this method gets many advantages such as reducing current ripple, thermal loss, and noises and improving control performances. Theoretical approach to this voltage-current controller is performed, and the results are presented.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1610-1620
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• 2015

A major problem in conventional multilevel inverter is that an increase in power semiconductor switches causes an increase in cost and switching losses of the inverter. The multicarrier strategy adopted for the multilevel inverters has become more popular due to reduced cost, lower harmonic distortion, and higher voltage capability than the conventional switching strategy applied to inverters. Various topologies and modulation strategies have been reported for utility and drive applications. Level shifted based pulse width modulation techniques are proposed to investigate the performance of the multilevel inverter. The proposed work focuses on reducing the utilized switches so that the cost and the switching losses of the inverter do not go up and the consistent efficiency could be achieved. This paper presents the detailed analysis of these topologies. The analysis is based on the number of switches, DC sources, output level, maximum voltage, and the efficiency. As an illustration, single phase cascaded multilevel inverter topologies are simulated using MATLAB/SIMULINK and the experimental results demonstrate the viability of these inverters.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• Journal of Power Electronics
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• 제15권6호
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• pp.1517-1523
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• 2015

The wavelet PWM (WPWM) technique has been applied in two-level inverters successfully, but directly applying the WPWM technique to three-level inverters is impossible. This paper proposes a WPWM technique suitable for a single-phase three-level inverter. The work analyzes the control strategy with the WPWM and obtains the design of its parameters. Compared with the SPWM technique for a single-phase three-level inverter under the same conditions, the WPWM can obtain high magnitudes of the output fundamental frequency component, low total harmonic distortion, and simpler digital implementation. The feasibility experiment is given to verify of the proposed WPWM technique.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 추계학술대회 논문집
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• pp.121-122
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• 2014

멀티 레벨 인버터는 높은 출력 전압을 갖으며, 낮은 THD(Total harmonic distortion)를 요구하는 시스템에 적합하다. 그 중 cascaded H-brige 멀티레벨 인버터는 H-bridge 셀별 관리가 쉽고, 레벨 수를 증가시키기 쉽다는 장점 때문에 많이 이용되어 왔다. 본 논문에서는 cascaded H-bridge 인버터의 기존 PI (proportional integral) 제어 기반 PWM (pulse width modulation)기법의 스위칭 패턴과 모델 예측 제어의 스위칭 패턴을 비교하고 모델예측 제어 시 셀 별 스위칭 패턴 균형을 위한 방법을 제안한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.169-173
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• 2005

In this paper, a comparative study of modified phase-angle, extinction-angle, and pulse width modulation control techniques for the purpose of power factor improvement of single-phase AC-AC voltage regulators have been illustrated as applied to a single-phase ac voltage converter by an example of the widely used single-phase induction motor as a dynamic load. Observations on power factor, displacement factor and total harmonic distortion factor are described and discussed on the basis of the simulated and measured results of this work.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.817-820
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• 2005

Dead-Time is necessary to prevent the shot circuit of the full bridge inverters in pulse width modulation. However the output voltage deviations is the result of the Dead-Time that decrease power from the out put voltage inverters. This paper presents the method that compensate power output voltage inverters loss in Dead-Time circuit for DC Motor Drives with full bridge voltage inverters. The compensation of Dead-Time method is a sample and a low-cost solution. The comparison between the test results and simulation by MATLAB&SIMULINK under the same condition is similar.