• Journal of Power Electronics
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• v.15 no.4
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• pp.994-1005
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• 2015

This paper presents a novel power control strategy for PWM current-source rectifiers (CSRs) in the stationary frame based on the instantaneous power theory. In the proposed control strategy, a virtual resistance based on the capacitor voltage feedback is used to realize the active damping. In addition, the proportional resonant (PR) controller under the two-phase stationary coordinate is designed to track the ac reference current and to avoid the strong coupling brought about by the coordinate transformation. The limitations on improving steady-state performance of the PR controller is investigated and mitigated using a cascaded lead-lag compensator. In the z-domain, a straightforward procedure is developed to analyze and design the control-loop with the help of MATLAB/SISO software tools. In addition, robustness against parameter variations is analyzed. Finally, simulation and experimental results verify the proposed control scheme and design method.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.409-415
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• 2012

This paper presents a new software-based on-line dead-time compensation technique for a single-phase grid-connected photovoltaic (PV) inverter system. To prevent a short circuit in the inverter arms, a switching delay time must be inserted in the pulse width modulation (PWM) signals. This causes the dead-time effect, which degrades the system performance around zero-crossing point of the output current. To reduce the dead-time effect around the zero-crossing point of grid current, a harmonic mitigation of grid current is used as an additional part of the synchronous frame current control scheme. This additional task mitigates the harmonic components caused by the dead-time from the grid current. Simulation and experimental results are shown to verify the effectiveness of the proposed dead-time compensation method in the single-phase grid-connected inverter system.

• Journal of Power Electronics
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• v.17 no.3
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• pp.641-652
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• 2017

This paper proposes a cost-effective topology to drive a three-phase open-end load based on a five-leg indirect matrix converter (IMC) and a space vector modulation (SVM) method. By sharing an inverter leg with two load terminals, the proposed topology can reduce the number of power switches when compared to topologies based on a direct matrix converter or a six-leg IMC. The new SVM method uses only the active vectors that do not produce common-mode voltage (CMV), which results in zero CMV across the load phase and significantly reduces the peak value of the CMV at the load terminal. Furthermore, the proposed drive system can increase the voltage transfer ratio up to 1.5 and provide a superior performance in terms of an output line-to-line voltage with a three-level pulse-width modulation waveform. Simulation and experimental results are given to verify the effectiveness of the proposed topology and the new SVM method.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.150-158
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• 2017

This study proposes a new pulse-width modulation switching pattern for the low conduction loss of a three-level neutral point clamped (NPC)-based dual-active bridge (DAB) converter. The operational principle for a bidirectional power conversion is a phase-shift modulation. The conventional switching method of the three-level NPC-based DAB converter shows a symmetric switching pattern. This method has a disadvantage of high root-mean-square (RMS) value of the coupling inductor current, which leads to high conduction loss. The proposed switching method shows an asymmetrical pattern, which can reduce the RMS value of the inductor current with lower conduction loss than that of the conventional method. The performance of the proposed asymmetrical switching method is theoretically analyzed and practically verified using simulation and experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.166-174
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• 2017

This study proposes a compensation method for the dead-time effects on a single-phase grid-connected inverter. Dead time should be considered in the pulse-width modulation gating signals to prevent the simultaneous conduction of switching devices, considering that a switching device has a finite switching time. Consequently, the output current of the grid-connected inverter contains odd-numbered harmonics because of the dead time and the nonlinear characteristics of the switching devices. The effects of dead time on output voltage and current are analyzed in this study. A new compensation algorithm based on second-order generalized integrator is also proposed to reduce the dead-time effect. Simulation and experimental results validate the effectiveness of the proposed compensation algorithm.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.572-579
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• 1995

Most of conventional ultrasonic transducers are constructed to generate either longitudinal or shear waves, but not both of them. We investigate the mechanism of dual mode transducers that generate both of the longitudinal and shear waves simultaneously with single PZT element. The study is aimed to find the optimally desired cut by examining the anisotropic piezoelectric properties. Theory predicts that a mixed P/S mode transducer can be constructed using a rotated Z-cut of PZT piezoelectric ceramics. We study the performance of a PZT element as a function of its rotation angle so that its efficiency is optimized to excite the two waves as much as equally strong. The results are verified by the waveform in pulse-echo computer simulation and experiments. When the transducer is subjected to impedance analysis, it shows two thickness mode resonances, each of which being a mixed P/S thickness mode. By examining wave speeds on E transmitter delay line receiver setup, it is confirmed that the transducer can transmit and detect both longitudinal and shear wave simultaneously.

• Journal of the Korean Society of Industry Convergence
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• v.20 no.2
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• pp.115-124
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• 2017

This paper aims to develop an SMPS topology for handling a high range of input voltages based on a DC-DC flyback converter circuit. For this purpose, 2 capacitors of the same specifications were serially connected on the input terminal side, with a flyback converter of the same circuit configuration serially connected to each of them, so as to achieve high input voltage and an effect of dividing input voltage. The serially connected flyback converters have the transformer turn ratio of 1:1, so that each coil is used for the winding of a single transformer, which is a characteristic of doubly-fed configuration and enables the correction of input capacitor voltage imbalance. In addition, a pulse transformer was designed and fabricated in a way that can achieve the isolation and noise robustness of the PWM output signal of the PWM controller that applies gate voltage to individual flyback converter switches. PSIM simulation was carried out to verify such a structure and confirm its feasibility, and a 100W class stack was fabricated and used to verify the feasibility of the proposed high voltage SMPS topology.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1523-1534
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• 2017

A Current Error Space Phasor (CESP) based hysteresis controller with online computation of the boundary for two-level inverter fed Induction Motor (IM) drives is presented in this paper. The stator voltages estimated along the ${\alpha}$-and ${\beta}$-axes and the orthogonal current error components of the motor are used in the online computation of the hysteresis boundary. All of the inherent benefits of space phasor based hysteresis controllers such as its quick dynamic response and nearby voltage vector switching are present in the proposed scheme with the added benefit of suppressing switching frequency variations. The similarity in the frequency spectrum of the phase voltage obtained at the output of the inverter using the proposed scheme and Bus Clamping Pulse Width Modulation (BCPWM) based drive is justified with the help of extensive MATLAB SIMULINK simulations. The controller is experimentally verified with a three phase, 2.2 kW IM drive for steady state and transient conditions and the obtained results match the simulation results.

• Journal of Power Electronics
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• v.17 no.4
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• pp.923-932
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• 2017

This paper proposes a novel scheme which can compensate the common-mode voltage (CMV) for five-level active neutralpoint clamped (5L-ANPC) inverters, which is based on modifying the space vector pulse width modulation (SVPWM) and adding an auxiliary leg to the inverter. For the modified SVPWM, only the 55 voltage vectors producing low CMV values among the 125 possible voltage vectors are utilized, which varies over the three voltage levels of $-V_{dc}/12$, 0 V, and $V_{dc}/12$. In addition, the compensating voltage, which is injected into the 5L-ANPC inverter system to cancel the remaining CVM through a common-mode transformer (CMT) is generated by the additional NPC leg. By the proposed method, the CMV of the inverter is fully eliminated, while the utilization of the DC-link voltage is not decreased at all. Furthermore, all of the DC-link and flying capacitor voltages of the inverter are well controlled. Simulation and experimental results have verified the validity of the proposed scheme.

• Journal of Power Electronics
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• v.17 no.4
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• pp.933-941
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• 2017

In this paper an improved low frequency selective harmonic elimination-PWM (SHE-PWM) technique for Cascaded H-bridge (CHB) converters is proposed. The proposed method is able to eliminate low order harmonics from the output voltage of the converter for a wide range of modulation indices. To solve SHE-PWM equations, especially for low modulation indices, a modified method is used which employs either the positive or negative voltage polarities of H-bridge cells to increase the freedom degrees of each cell. Freedom degrees of the switching angles are also used to increase the range of available solutions for non-linear SHE equations. The proposed SHE methods can successfully eliminate up to $25^{th}$ harmonic from a 7-level output voltage by using just nine switching transitions or a 150 Hz switching frequency. To confirm the validity of the proposed method, simulation and experimental results have been presented.