• Journal of Advanced Marine Engineering and Technology
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• v.3 no.1
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• pp.19-31
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• 1979

Recently the adaptive control system, which keeps the control system always optimal by adjusting the control parameters automatically according to the variations of the plant parameters, have become very important in the field of control engineering. The adaptive control systems are usally composed of the plant identification, the decision of the optimal control parameters, and the adjustment of the control parameters. This paper deals with a method of the adaptive control system when PI or PID controller is used in the feed back control system. Its controlled object (the plant) is assumed to be described by the transfer function of $\frac{ke^{-LS}}{1+TS}$ where k, T and L are steady state gain, time constant and pure dead time respectively, and their values are variable in accordance with the change of environmental circumstance. It has been known that a pseudo-random binary signal is quite effective for the measurement of an impulse response of a plant. In adaptive control systems, however, the impulse response itself is not appropriate to determine the control parameters. In this paper, the authors propose a method to estimate directly the parameters of the plant k, T and L by means of the correlation technique using 3 level M-sequence signal as a test signal. The authors also propose a method to determine the optimal parameters of the PI or PID controller in the sense of minimizing the square integral of the control error in the feed back control system, and the values of the optimal parameters are computed numerically for various values of T and L, and the results are examined and compared with those of the conventional methods. Finally the above-mentioned two methods are combined and an algorithm to struct an adaptive control system is suggested. The experiments for the indicial responses by means of both the model of the temperature control system using SCR actuater and the analog simulations have shown good results as expected, and the effectiveness of the proposed method is verified. The M-sequence generator and the time delay circuit, which are manufactured for the experiments, are operated in quite a good condition.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.533-540
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• 2021

To evaluate the performance of a system, one-dimensional 3-neighborhood cellular automata(CA) based pseudo-random generators are widely used in many fields. Although two-dimensional CA and one-dimensional 5-neighborhood CA have been applied for more effective key sequence generation, designing symmetric one-dimensional 5-neighborhood CA corresponding to a given primitive polynomial is a very challenging problem. To solve this problem, studies on one-dimensional 5-neighborhood CA synthesis, such as synthesis method using recurrence relation of characteristic polynomials and synthesis method using Krylov matrix, were conducted. However, there was still a problem with solving nonlinear equations. To solve this problem, a symmetric one-dimensional 5-neighborhood CA synthesis method using a transition matrix of 90/150 CA and a block matrix has recently been proposed. In this paper, we detail the theoretical process of the proposed algorithm and use it to obtain symmetric one-dimensional 5-neighborhood CA corresponding to high-order primitive polynomials.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1884-1891
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• 2012

In this paper, we design the sliding correlator SS transceiver which supports short message service. We also analyze the PN code acquisition circuit that is essential for spread spectrum receiver. Using Maxplus II tool provided by altera Co., Ltd, we have designed PN code generator, and sliding correlator for PN code acquisition. Then, they have been made into FPGA by way of EPM7064SLC44-10 - a chip of Altera Co., Ltd. Additionally, we have designed delay clock circuit which is faster than the clock of Tx PN clock, designed switching circuit to control the clock rate and data demodulation circuit. The performance of the transceiver is evaluated from the experimental results. Especially, the performance of PN code acquisition accomplished by sliding correlator which is very important to evaluate spread spectrum receiver is evaluated with the comparison of the lock states.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.28-36
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• 2009

Time-memory trade-off (TMTO) cryptanalysis proposed by Hellman can be applied for the various crypto-systems such as block ciphers, stream ciphers, and hash functions. In this paper, we propose a novel method to reduce memory size for storing TMTO tables. The starting points in a TMTO table can be substituted by the indices of n-bit samples from a sequence in a family of pseudo-random sequences with good cross-correlation, which results in the reduction of memory size for the starting points. By using this method, it is possible to reduce the memory size by the factor of 1/10 at the cost of the slightly increasing of operation time in the online phase. Because the memory is considered as more expensive resource than the time, the TMTO cryptanalysis will be more feasible for many real crypto systems.

• Korean Journal of Optics and Photonics
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• v.31 no.5
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• pp.218-222
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• 2020

In this paper, we have experimentally demonstrated a 2-kW-class spectrally-beam-combined laser with high beam quality, using narrow-linewidth ytterbium-doped polarization-maintaining fiber amplifiers. Five fiber amplifiers with different center wavelengths were implemented for the spectrally-beam-combined laser. The center wavelengths of the five amplifiers were 1062, 1063, 1064, 1065, and 1066 nm, respectively. A phase-modulated laser diode was used as a seed source for each amplifier. The seed sources were modulated by filtered pseudorandom-bit-sequence (PRBS) signals 5 GHz in linewidth. The polarization-maintaining large-mode-area fiber with a core size of 30 ㎛ was used as a delivery fiber to mitigate the stimulated Brillouin scattering (SBS) effect. The laser beams from five amplifiers were spectrally combined by a multilayer dielectric diffraction grating. The maximum output power and beam quality M² of the combined laser were measured to be 2.3 kW and 1.74, respectively.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.