• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.24-25
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• 2008

An Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for RF (Radio Frequency) integrated circuits (ICs). This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF applications. Key issues in RF ESD protection, design methods, and RF ESD protection solutions are discussed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• Journal of Communications and Networks
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• v.9 no.1
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• pp.93-104
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• 2007

Traffic grooming, in which low-rate circuits are multiplexed onto wavelengths, with the goal of minimizing the number of add-drop multiplexers (ADMs) and wavelengths has received much research attention from the optical networking community in recent years. While previous work has considered various traffic models and network architectures, protection requirements of the circuits have not been considered. In this paper, we consider survivable traffic grooming, or grooming traffic which contains a mix of circuits that need protection and that do not need protection. We assume a unidirectional ring network with all-to-all symmetric traffic with $t\geq1$ circuits between each node pair, of which s require protection. As it turns out, survivable traffic grooming presents a significant tradeoff between the number of wavelengths and the number of ADMs, which is almost non-existent in non-survivable traffic grooming for this type of traffic. We explore this tradeoff for some specific cases in this paper. We also present some new results and solution methods for solving certain non-survivable traffic grooming problems.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of the Korean Society of Industry Convergence
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• v.21 no.6
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• pp.265-271
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• 2018

DC-DC buck converter is a critical building block in the power management integrated circuit (PMIC) architecture for the portable devices such as cellular phone, personal digital assistance (PDA) because of its power efficiency over a wide range of conversion ratio. To ensure a safe operation, avoid unexpected damages and enhance the reliability of the converter, fully-integrated protection circuits such as over voltage protection (OVP), under voltage lock out (UVLO), startup, and thermal shutdown (TSD) blocks are designed. In this paper, these three fully-integrated protection circuit blocks are proposed for use in the DC-DC buck converter. The buck converter with proposed protection blocks is operated with a switching frequency of 1 MHz in continuous conduction mode (CCM). In order to verify the proposed scheme, the buck converter has been designed using a 180 nm CMOS technology. The UVLO circuit is designed to track the input voltage and turns on/off the buck converter when the input voltage is higher/lower than 2.6 V, respectively. The OVP circuit blocks the buck converter's operation when the input voltage is over 3.3 V, thereby preventing the destruction of the devices inside the controller IC. The TSD circuit shuts down the converter's operation when the temperature is over $85^{\circ}C$. In order to verify the proposed scheme, these protection circuits were firstly verified through the simulation in SPICE. The proposed protection circuits were then fabricated and the measured results showed a good matching with the simulation results.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.674-676
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• 2008

An electrostatic discharge (ESD) or a noise supplied from the outside has an effect on communication between the timing controller (TCON) and the memory element (EEPROM) through the interface between the timing controller and the memory element in liquid crystal displays (LCD). Therefore, we must apply ESD protection methods to LCD operating circuits for a normal operation. Our ESD protection circuit is to prevent from bi-directional communication errors between TCON and EEPROM due to an electrostatic discharge (ESD).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.8-14
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• 1991

A new algorithm for calculation of overcurrent and overvoltage at load for parallel two-wire transmission line with nonlinear protection circuits induced by and external electromagnetic pulse is suggested. The rigorous solution is obtained for a particular type of the incident waveform and protection circuit. The validity of our algorithm is checked by comparing numerical results to the analytic solution in the particular case.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1063-1064
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• 2008

In this paper, two kinds of the protection circuits are proposed and simulated to verify their performances. One is an over current protection circuit, and the other is a no load protection circuit which reduces power consumption. These protection circuits of an LED drive circuit can reduce power consumption and prevent to damage the elements.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1067-1068
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• 2008

An inverter for driving flat fluorescent lamp(FFL) with various protection circuits using micro controller(Micom) is proposed in this paper. The inverter will be shut down if the fault operating conditions such as open lamp, over current and over voltage are detected.