• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.11
• /
• pp.1-11
• /
• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.12
• /
• pp.13-22
• /
• 1998

In this paper, we propose a high-performance BICS(built-in current sensor) which is fabricated in 0.8${\mu}{\textrm}{m}$ single-poly two-metal process for IDDQ testing of CMOS VLSI circuit. The CUT(circuit under test) is 4-bit full adder with a bridging fault. Using two nMOSs that have different size, two bridging faults that have different resistance values are injected in the CUT. And controlling a gate node, we experimented various fault effects. The proposed BICS detects the faulty current at the end of the clock period, therefore it can test a CUT that has a much longer critical propagation delay time and larger area than conventional BICSs. As expected in the HSPICE simulation, experimental results of fabricated chip demonstrated that the proposed BICS can exactly detect bridging faults in the circuit.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.1
• /
• pp.51-56
• /
• 1981

A new I2L process for a high performance I2L structure is proposed. The modifiedstructure consists of a heavily doped extrinsic base and lowly doped intrinsic base where the collector regions are self-alignment with the intrinsic base regions. The proposed process untilizes spin-on sources as the diffusion sources and the self-alignment of collectors is achieved by using the hardened spin-on source as a diffusion mask. Test devices including a 13-stage ring oscillator have been fabricated by the proposed process on n/n+ silicon wafers with 6.5$\mu$m epitaxial layer. The maximum upward current gain of npn transistors is 8 for a three collector I2L cell. The speed-power product and minimum propagation delay for a one collector structure are 3.5 pJ and 50 ns, respectively.

• Smart Structures and Systems
• /
• v.10 no.3
• /
• pp.229-251
• /
• 2012

Guided waves have shown a great potential for structural health monitoring (SHM) applications. In contrast to traditional non-destructive testing (NDT) methodologies, a key element of SHM approaches is the high process of automation. The monitoring system should decide autonomously whether the host structure is intact or not. A basic requirement for the realization of such a system is that the sensors are permanently installed on the host structure. Thus, baseline measurements become available that can be used for diagnostic purposes, i.e., damage detection, localization, etc. This paper contributes to guided wave-based inspection in anisotropic materials for SHM purposes. Therefore, computational strategies are described for both, the solution of the complex equations for wave propagation analysis in composite materials based on exact elasticity theory and the popular global matrix method, as well as the underlying equations of two active damage localization algorithms for anisotropic structures. The result of the global matrix method is an angular and frequency dependent wave velocity characteristic that is used subsequently in the localization procedures. Numerical simulations and experimental investigations through time-delay measurements are carried out in order to validate the proposed theoretical model. An exemplary case study including the calculation of dispersion curves and damage localization is conducted on an exemplary unidirectional composite structure where the ultrasonic signals processed in the localization step are simulated with the spectral element method. The proposed study demonstrates the capabilities of the proposed algorithms for accurate damage localization in anisotropic structures.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.8 no.2
• /
• pp.91-99
• /
• 2009

Mobile WiMAX is an emerging technology that can provide ubiquitous Internet access. To provide seamless service in mobile WiMAX environment, delay or disruption in dealing with mobility must be minimized. However offering seamless services on IEEE 802.16e networks is very hard due to long handover latency both in layer 2 and 3. In this paper, we propose a fast cross-layer handover scheme based on prediction algorithm. With the help of the prediction, layer-3 handover activities are able to occur prior to layer-2 handover, and therefore, total handover latency can be reduced. The experiments conducted with system parameters and propagation model defined by WiMAX Forum demonstrate that the proposed method predicts the future signal level accurately and reduces the total handover latency.

• 한국태양에너지학회:학술대회논문집
• /
• 2012.03a
• /
• pp.325-330
• /
• 2012

A single-phase PVPCS(photovoltaic power conditioning system) that contains a single phase dc-ac inverter tends to draw an ac ripple current at twice the out frequency. Such a ripple current may shorten passive elements life span and worsen output current THD. As a result, it may reduce the efficiency of the whole PVPCS system. In this paper, the ripple current propagation is analyzed, and two methods to reduce the ripple current are proposed. Firslyt, this paper presents notch filter with IP voltage controller to reject specific current ripple in single-phase PVPCS. The notch filter can be designed that suppress just only specific frequency component and no phase delay. The proposed notch filter can suppress output command signal in the ripple bandwidth for reducing output current THD. Secondly, for reducing specific current ripple, the other method is feed-forward compensation to incorporate a current control loop in the dc-dc converter. The proposed notch filter and feed-forward compensation method have been verified with computer simulation and simulation results obtained demonstrate the validity of the proposed control scheme.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.26 no.1
• /
• pp.89-96
• /
• 2016

TDOA(time delay of arrival) position estimate from acoustic measurement of artillery shell impact is studied in order to develop a targeting evaluation system. Impact position is calculated from the intersections of hyperbolic estimates based on the least square Taylor series method. The mathematical process of Taylor series estimation is known to be robust. However, the concern lays with the accuracy because it is sensitive to the bias caused by the randomness of measurement situation. The measurement error typically occurs from the distortion of waveform, change of travelling path, and sensor position error. For outdoor measurement, a consideration should be made on the atmospheric condition such as temperature and wind which can possibly change the trajectories of rays of sound. It produces wrong propagation time events accordingly. Ray tracing and optimization techniques are introduced in this study to minimize the bias induced by the ray of sound. The numerical simulation shows that the atmospheric correction improves the estimation accuracy.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.5
• /
• pp.737-748
• /
• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

• The Journal of Information Technology
• /
• v.6 no.4
• /
• pp.11-23
• /
• 2003

We proposes that Design of the Digital Neuron Processor and Development of the Algorithm for the real time object recognition in the making Automatic system which uses the residue number system making the high speed operation possible without carry propagation, in this paper. Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed. The Designed circuits are descripted by C language and VHDL and synthesized by Compass tools. Finally, the designed processor is fabricated in 0.8${\mu}m$ CMOS process. Result of simulations shows that critical path delay time is about 19nsec and operation speed is 0.6nsec and the size can be reduced to 1/2 times co pared to the neural networks implemented by the real number operation unit. The proposed design the digital neuron processor can be implemented of the object recognition in the making Automatic system with desired real time processing.

• Journal of Korean Tunnelling and Underground Space Association
• /
• v.5 no.3
• /
• pp.251-260
• /
• 2003

Tunnel blasting has been performed with V-cut to investigate the characteristics. Blasting vibrations were measured at two directions, the proceed direction and side direction. Propagation characteristics were determined by regression analysis; square root scaled distance and cube root scaled distance with maximum charge per delay of the blast. Testing result, The cross point was 62m in the allowable vibration velocity of 3mm/sec and 46m in 5mm/sec. Also, vibration level with measuring point was highest and decayed fastest, adapting to cube root scaled distance, for the proceed direction on ground.