• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.9
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• pp.663-670
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• 1988

Advances in VLSI technology have made it possible to have a larger number of processing elements to be included in highly parallel processor system. A system with a large number of processing elements and memory requires a complex data path. Multistage Interconnection networks(MINS) are useful in providing programmable data path between processing elements and memory modules in multiprocessor system. In this thesis, the performance of MINS for the star network has been analyzed and compared with other networks, such as generalized shuffle network, delta network, and referenced crossbar network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1346-1355
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• 2005

Recently, the development of passive optical networks (PON) for FTTH (Fiber-To-The-Home) have been actively conducted. In PON, a burst-mode transceiver is one of key modules. In this paper, we have made the protype module of a 155.52 Mpbs optical burst-mode transceiver with commercially available chips and then have measured the performance. Also, a new method of burst-mode clock recovery have been proposed. The burst-mode clock recovery implemented by using CPLD(Complex Programmable Logic Device) has coupled with the above burst-mode transceiver and has been tasted.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.5
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.16-23
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• 2022

Cardiac disease is the most common cause of death worldwide. Therefore, detection and classification of electrocardiogram (ECG) signals are crucial to extend life expectancy. In this study, we aimed to implement an artificial intelligence signal recognition system in field programmable gate array (FPGA), which can recognize patterns of bio-signals such as ECG in edge devices that require batteries. Despite the increment in classification accuracy, deep learning models require exorbitant computational resources and power, which makes the mapping of deep neural networks slow and implementation on wearable devices challenging. To overcome these limitations, spiking neural networks (SNNs) have been applied. SNNs are biologically inspired, event-driven neural networks that compute and transfer information using discrete spikes, which require fewer operations and less complex hardware resources. Thus, they are more energy-efficient compared to other artificial neural networks algorithms.

• Journal of Communications and Networks
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• v.3 no.4
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• pp.317-323
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• 2001

Traditional configuration management involves complex labor-intensive processes performed by experts. The configuration tasks such as installing or reconfiguring a system, provisioning network services and allocating resources typically involve a large number of activities involving multiple network elements. The network elements may be associated with proprietary configuration management instrumentation and may also be spread across heterogeneous network domains thereby increasing the complexity of configuration management. This paper introduces an architecture for the self-configuration of networks (SELFCON). The proposed architecture involves a directory server, which is uses to maintain configuration information. The configuration information stared in the directory server is modeled using the standard DEN specification thereby allowing effective exchange of network, system and configuration management data among heterogeneous management domains. SELFCON associates configuration intelligence with the components of the network, rather than limit it to a centralized management station. The network elements are notified about related changes in configuration policies, based upon which, they perform self-configuration. SELFCON is able to provide automation of configuration management and also an effective unifying framework for enterprise management.

• Electronics and Telecommunications Trends
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• v.15 no.4 s.64
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• pp.1-11
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• 2000

프로그래머블 네트워크 기술은 사용자의 요구에 따라 빠르게 새로운 서비스를 생성, 전개하고자 하는 필요에 따라 발전하였다. 프로그래머블 네트워크 기술은 새로운 구조와 서비스 및 프로토콜들을 네트워크에 적용하기 위해 네트워크의 programmability를 제어하고 안전하게 실행하는 방법이다. 네트워크 programmability 증진을 위하여 전송 하드웨어와 제어 소프트웨어의 분리, 개방형 프로그래머블 네트워크 인터페이스 제공, 네트워킹 기반구조의 가상화 촉진 같은 하드웨어상에 상이한 네트워크 구조의 공존 및 자원분할 기술 등이 연구되고 있다. 이 글에서는 프로그래머블 네트워크 기술 분야의 연구 프로젝트를 살펴보고 프로그래머블 통신 추상화, programmability 수준, 프로그래밍 방법론 등의 특징을 비교 분석하였다.

• Electrical & Electronic Materials
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• v.11 no.11
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• pp.53-65
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• 1998

Planar lightwave circuits (PLCs) provide various important devices for optical wavelength division multiplexing (WDM) systems, subscriber networks and etc. This paper reviews the recent progress and future prospects of PLC technologies including arrayed-waveguide grating multiplexers, optical add/drop multiplexers, programmable dispersion equalizers and hybrid optoelectronics integration technologies.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.98-107
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• 1996

In this paper, we propose a scheme that maps the time-delay neural network (TDNN) into the neurocomputer called EMIND-II which has the wavefront toroidal mesh-array structure. This neurocomputer is scalable, consists of many timeshared virtual neurons, is equipped with programmable on-chip learning, and is versatile for building many types of neural networks. Also we define the programming model of this array and derive the parallel algorithms about TDNN for the proposed neurocomputer EMIND-II. In addition, the computational complexities for the parallel and serial algorithms are compared. Finally, we introduce an application of this neurocomputer to word recognition.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.1
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• pp.1-17
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• 2016

The separated management and operation of commercial IP/optical multilayer networks makes network operators look for a unified control plane (UCP) to reduce their capital and operational expenditure. Software-defined networking (SDN) provides a central control plane with a programmable mechanism, regarded as a promising UCP for future optical networks. The general control and scheduling mechanism in SDN-based optical burst switching (OBS) networks is insufficient so the controller has to process a large number of messages per second, resulting in low network resource utilization. In view of this, this paper presents the burst-flow scheduling mechanism (BFSM) with a proposed scheduling algorithm considering channel usage. The simulation results show that, compared with the general control and scheduling mechanism, BFSM provides higher resource utilization and controller performance for the SDN-based OBS network in terms of burst loss rate, the number of messages to which the controller responds, and the average latency of the controller to process a message.