• Title/Summary/Keyword: programmable

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Microcode-based Output Pulse Generation for Remote Controller Application (원격조종장치를 위한 마이크로코드방식의 출력펄스발생회로)

  • 장현수;조경록;유영갑
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.10
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    • pp.1527-1536
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    • 1993
  • A new transmitter circuit for remote controllers is designed to provide flexibility and expandibility in function. The circuit employs a microcode approach to accept various code format, length and pulse widths through programming, and the precessing logics is eliminated to reduce its size. The circuit was Implemented using FPGA(Field Programmable Gate Array) and it was found to operate successfully).

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A Study of amorphous chalcogenide thin films for manufacturing PMC device (PMC 소자 제작을 위한 비정질 칼코게나이드 박막 연구)

  • Park, Ju-Hyun;Kang, Jj-Soo;Han, Chang-Jo;Lee, Dal-Hyun;Chung, Hong-Bay
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.354-354
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    • 2010
  • In this study, we studied the nature of thin films formed by photodoping chalcogenide materials with for use in programmable metallization cell devices, a type of ReRAM. We investigated the resistance of Ag-doped chalcogenide thin films varied in the applied voltage bias direction from about $1\;M{\Omega}$ to several hundreds of $\Omega$. As a result of these resistance change effects, it was found that these effects agreed with PMC-RAM. The results imply that a Ag-rich phase separates owing to the reaction of Ag with free atoms from the chalcogenide materials.

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A Design of Programmable Dual Slope A/D Converter by Single Chip Microprocessor (싱글칩 마이크로프로세서에 의한 프로그래머블 2중 적분형 A/D 변환기의 개발)

  • Choi, G.S.;Park, C.w.
    • Proceedings of the KIEE Conference
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    • 1993.11a
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    • pp.335-337
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    • 1993
  • Offset voltage and drift characteristics of operational amplifier are critical factor to precision AID conversion System. In this study, a method is suggested to design the programmable A/D conversion system which has high resolution and low drift characteristics. First, hardware was designed to reduce the offset voltage of integrator and comparator, and analog switches are connected to reduce the drift characteristics of operational amplifier. And then, a calibration software technique was performed to obtain the stable data from A/D converter. The main advantage of our method is high precision A/D converter can be constructed with low cost and high confidence. Therefore proposed method is expected to be used in the industrial field where a high precision measurement is required.

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Development of a FA network model system (FA용 network 모델 시스템 개발 연구)

  • Kim, C. H.;Chung, H. J,;Choi, Y.;Ha, J. H.;Han, D. W.;Chae, Y. D.
    • 제어로봇시스템학회:학술대회논문집
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    • 1988.10a
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    • pp.396-400
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    • 1988
  • This paper described network model system for FA with programmable devices such as PLC, CNC, Robot which basis on the MAP protocol and constructed with the broadband 1OMbps cables. Developed systems can comniunicate and control with programmable devices. Such systems we called are Remote PLC Control System, Remote CNC Control System, Remote Robot Control System.

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Multithread video coding processor for the videophone (동영상 전화기용 다중 스레드 비디오 코딩 프로세서)

  • 김정민;홍석균;이일완;채수익
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.5
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    • pp.155-164
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    • 1996
  • The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

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A study on implementation digital programmable CNN with variable template memory (가변적 템플릿 메모리를 갖는 디지털 프로그래머블 CNN 구현에 관한 연구)

  • 윤유권;문성룡
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.10
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    • pp.59-66
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    • 1997
  • Neural networks has widely been be used for several practical applications such as speech, image processing, and pattern recognition. Thus, a approach to the voltage-controlled current source in areas of neural networks, the key features of CNN in locally connected only to its netighbors. Because the architecture of the interconnection elements between cells in very simple and space invariant, CNNs are suitable for VLSI implementation. In this paper, processing element of digital programmable CNN with variable template memory was implemented using CMOS circuit. CNN PE circuit was designe dto control gain for obtaining the optimal solutions in the CNN output. Performance of operation for 4*4 CNN circuit applied for fixed template and variable template analyzed with the result of simulation using HSPICE tool. As a result of simulations, the proposed variable template method verified to improve performance of operation in comparison with the fixed template method.

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Development of the Digital Controller for High Precision Digital Power Supply (고정밀전원장치를 위한 디지털 제어기 개발)

  • Ha, K.M.;Lee, S.K.;Kim, Y.S.
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2006.06a
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    • pp.249-250
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    • 2006
  • In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

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Processing control of bulk ALC using PLC (Programmable logic controller를 이용한 bulk ALC 처리 공정 제어)

  • 황윤상
    • 제어로봇시스템학회:학술대회논문집
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    • 1992.10a
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    • pp.67-70
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    • 1992
  • 1930년 스웨덴에서 개발에 성공, 네덜란드에서 더욱 발전시킨 ALC(Autoclaved Light-weignt Concrete의 약칭) 는 가볍고, 견고하고, 그리고 시공이 간편한 경제적인 요건들을 충족시키는 건축자재로 세계적으로 널리 사용되고 있으며 , 국내에서는 불과 수년 전부터 연구 개발되고 있는 실정이다. ALC 란 시멘트와 규사, 생석회등 무기질 원료를 고온,고압으로 증기 양생시킨 경량의 기포 콘크리트 제품을 통칭한 것이다. ALC공정은 bulk ALC를 생산하는 batch공정과 이 bulk ALC에 대한 처리 공정으로 크게 나눌 수가 있으며 여기에서는 bulk ALC 처리 공정을 side shield treatment, anti-corrosion treatment, curing grate transferer, cutting station, curing car transportation, autoclave traveling platform, 및 packing 의 공정으로 세분하여 각 공정개요 소개 및 PLC(Programmable Logic Controller의 약칭)를 이용한 제어 system에 대하여 설명하고자 한다.

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A Study of Algorithm for Digital Technology (디지털 기술의 알고리즘에 관한 연구)

  • Youn, Choong-Mo;Kim, Jae-Jin
    • Journal of Digital Contents Society
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    • v.10 no.4
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    • pp.633-637
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    • 2009
  • In this paper, we present the reuse module library generating algorithm and register-transfer (RT) library generating algorithm considering the power consumption of reuse module for field-programmable gate array (FPGA) technology mapping in order to implement into the circuit for calculating power consumption. To realize the circuit of calculation of power consumption, the FPGA is selected. Considering lookup table (LUT) conditions of selected FPGA, technology mapping process is conducted to minimize the total power consumption. With these information, the circuit is realized using suitable given power consumption among allocated results of modules.

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Load Control Device for VVVF Inverter Testing (인버터 시험을 위한 부하제어 장치)

  • Kim, Gil-Dong;Lee, Han-Min
    • Proceedings of the KSR Conference
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    • 2007.05a
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    • pp.675-679
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    • 2007
  • The control method of programmable dynamometer for overall test of machine is to load reference torque which is computed from torque transducer into motor under test. But the torque information detected from torque transducer have a lot of noise when the load torque of moter is a small quantity or changing. Thus, torque transducer must have a low pass filter to detect a definite torque information. But The torque delay generated by filter with torque transducer occur a torque trouble for moter torque of programmable dynamometer. Therefore, this kind of system could not perform dynamic and nonlinear load. In this paper, the control method using the load torque observer without a measure for torque transducer is proposed. The proposed system improved the problem of the torque measuring delay with torque transducer, and the load torque is estimated by the minimal order state observer based on the torque component of the vector control induction moter. Therefore, the torque controller is not affected by a load torque disturbance.

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