• Journal of Animal Environmental Science
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• v.15 no.3
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• pp.241-250
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• 2009

This study was conducted to develop an prototype automatic feeder (AF) for growing-finishing pigs. The main components of AF were a feed storage hopper, a feeding motor, a feed agitator, a control box and a programmable IC, which were controlled by a personal computer. The powder type feed transfer rate of AF was average $9.83{\pm}0.4\;g\;s^{-1}$. In feeding test, growing pigs (Landrace) of about 43 kg live weight were used in the study, and was fed over a 6 weeks in pens with solid concrete floors. For feeding trials with AF, the operation time of the feeding motor was set to 2, 3, 4, 5, and 6 seconds per feeding. Pigs frequently used AF from 05:00 to 11:00 and from 11:00 to 17:00 without relationship to the operation time of the feeding motor. The AF operation time of the feeding motor to minimize feed loss was between 2 and 4 seconds. Pigs fed with AF had same or slightly higher average daily gam (0.8~0.9 kg) than that with a commercial feeder, and average daily feed intake (2.76~2.93 kg) and feed conversion ratio (3.10~3.66) of pigs fed with AF were same or lower than those with the commercial feeder except the operation time of the feeding motor set to 6 seconds. As a result, AF would help to use and improve the productivity of growing-finishing pigs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.120-130
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• 1999

In this paper, we show that the instantaneous phase current of the bifiler-wound hybrid stepping motor is dependent of lead angle and that the information of motor position is obtained from the instantaneous phase current at ${\pi}/2$ by the theoretical formular and its computer simulation results. From the facts, we design the microcontroller-based motor position sensorless controller of optimal lead angle, which generates the excitation pulses for the closed-loop drives. The controller is consist of microcontroller which has the function of A/D converter, programmable input/output timer, and the transfer table which has the values of optimal lead angle depending on motor velocity, and ROM which has the transfer table of the values of lead angle depending on velocity of motor and the values of instantaneous phase current at ${\pi}/2$. From the design of microcontroller-based controller, we minimize the external interface circuit and obtain flexibility by changing the contents of ROM transfer tables and the control software. We confirm that the designed controller drives the bifilar-wound hybrid stepping motor is the mode of optimal lead angle by comparing the instananeous phase current experimental results and computer simulation results.

• Journal of the HCI Society of Korea
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• v.1 no.1
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• pp.37-44
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• 2006

Specular reflections provide the visual feedback that describes the material type of an object, its local shape, and lighting environment. In photorealistic rendering, there have been a number of research available to render specular reflections effectively based on a local reflection model. In traditional cel animations and cartoons, specular reflections plays important role in representing artistic intentions for an object and its related environment reflections, so the shapes of highlights are quite stylistic. In this paper, we present a method to render and control stylized specular reflections using projective textures based on principal curvature analysis. Specifying a texture as a pattern of a highlight and projecting the texture on the specular region of a given 3D model, we can obtain a stylized representation of specular reflections. For a given polygonal model, a view point, and a light source, we first find the maximum specular intensity point, and then locate the texture projector along the line parallel to the normal vector and passing through the point. The orientation of the projector is determined by the principal directions at the point. Finally, the size of the projection frustum is determined by the principal curvatures corresponding to the principal directions. The proposed method can control the position, orientation, and size of the specular reflection efficiently by translating the projector along the principal directions, rotating the projector about the normal vector, and scaling the principal curvatures, respectively. The method is be applicable to real-time applications such as cartoon style 3D games. We implement the method by Microsoft DirectX 9.0c SDK and programmable vertex/pixel shaders on Nvidia GeForce FX 7800 graphics subsystems. According to our experimental results, we can render and control the stylized specular reflections for a 3D model of several ten thousands of triangles in real-time.

• Journal of Navigation and Port Research
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• v.26 no.4
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• pp.419-426
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• 2002

The conventional RTK-GPS technique has many problems which are permission using RF wireless modem, influence of geographic obstacle using radio wave, frequency interference, finiteness of frequency resources. To solve these problems, in this paper, we designed the DGPS correction message transmission system as a method to substitute the RF wireless modem of RTK-DGPS receiver. Then the interface module was designed and implemented for linkage of GPS receiver and mobile phone. As a result worked differential surveying using receiving correction message using RS-232C and communication control, users of mobile station were worked differential surveying correction between mobile phones. Interface module system was received the same result of precision which was compared RF wireless modem system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11B
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• pp.1303-1310
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• 2009

Glassless 3D display requires multiple images taken from different viewpoints to show a scene. The simplest way to get multi-view image is using multiple camera that as number of views are requires. To do that, synchronize between cameras or compute and transmit lots of data comes critical problem. Thus, generating such a large number of viewpoint images effectively is emerging as a key technique in 3D video technology. Image-based view synthesis is an algorithm for generating various virtual viewpoint images using a limited number of views and depth maps. In this paper, because the virtual view image can be express as a transformed image from real view with some depth condition, we propose an algorithm to compute multi-view synthesis from two reference view images and their own depth-map by stepwise duplex forward mapping. And also, because the geometrical relationship between real view and virtual view is repetitively, we apply our algorithm into OpenGL Shading Language which is a programmable Graphic Process Unit that allow parallel processing to improve computation time. We demonstrate the effectiveness of our algorithm for fast view synthesis through a variety of experiments with real data.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.124-130
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• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.

• Journal of Sensor Science and Technology
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• v.4 no.3
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• pp.80-88
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• 1995

This paper presents the fabrication of a metal-insulator-metal(MIM) antifuse structure consisting of insulators sandwiched between top electrode, Al, and bottom electrode, TiW and additionally studies on antifuse properties depending on the condition of insulator. The intermetallic insulators, prepared by means of sputter, comprised of silicon oxide and tantalum oxide. In such an antifuse structure, silicon oxide layer is utilized to decrease the leakage current and tantalum oxide layer, of which the dielectric strength is lower than that of silicon oxide, is also utilized to lower the breakdown voltage near 10V. Finally sufficient low leakage current, below 1nA, and low programming voltage, about 9V, could be obtained in antifuse device comprising $Al/Ta_{2}O_{5}(10nm)/SiO_{2}(10nm)/TiW$ structure and OFF resistance of 3$3.65M{\Omega}$ and ON resistance of $7.26{\Omega}$ could be also obtained. This $Ta_{2}O_{5}/SiO_{2}$ based antifuse structures will be promising for highly reliable programmable device.