• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.56-61
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• 2011

This paper describes design of a programmable frequency synthesizer for RF PLL with $0.18{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get programmable division ratio switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 1~14GHz frequency range.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.285-288
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• 2005

We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.

• Journal of Biomedical Engineering Research
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• v.36 no.5
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• pp.221-227
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• 2015

In this study, Multi-Array Electrodes (MAE) and Programmable Multi-channel Electrical Stimulator (PMES) were implemented for firing Trigger Points (TPs) of the patient with Myofascial Pain Syndrome (MPS). MAE has 25 Ag/AgCl electrodes arranged in the form of array ($5{\times}5$) fabricated with flexible pad, which are applicable to be easy-attached to curved specific region of the human body. PMES consisted of 25 channels. Each channel was to generate various electric stimulus patterns (ESPs) by changing the mono-phasic or bi-phasic of ESP, On/Off duration of ESP, the interval between ESP, and amplitude of ESP. PMES hardware was composed of Host PC, Stimulation Pattern Editing Program (SPEP), and Multi-channel Electrical Stimulator (MES). Experiments were performed using MAE and PMES as the following. First experiment was performed to evaluate the function for each channel of Sub- Micro Controller Unit (SMCU) in MES. Second experiment was conducted on whether ESP applied from each channel of SMCU in PMES was focused to the electrode set to the ground, after applying ESP being output from each channel of SMCU in PMES to MAE.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.265-269
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• 2009

Formal specification plays important roles in guaranteeing software safety of safety-critical systems such as nuclear power plant's digital control systems. We had developed a technique [1] which synthesizes Function Block Diagram(FBD) programs from NuSCR formal requirements specifications, but it did not be used widely as it had no automatic tool support. FBD is one of the programming languages for Programmable Logic Controllers(PLC) based system. This paper introduces a CASE tool, NuSCRtoFBD, developed to automate the synthesis procedure. The CASE tool NuSCRtoFBD can reduce a number of errors occurred in the process of manual FBD programming.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.753-758
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• 2002

In this paper, low voltage 3V CMOS programmable gain amplifier(PGA) for using in the transmitter and receiver of ADSL analog front-end is designed. The designed receive PGA is connected with 1.1MHz continuous lowpass fillet and controls the gain from 0dB to 30dB. And also the transmitter PGA is connected with 138KHz lowpass filter and controls the gain from -15dB to 0dB. The gain of All PGAs can be programmed by digital logic circuits and main controller. The designed PGAs are verified using HSPICE simulation with $0.35\mu{m}$ CMOS parameter.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.142-146
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• 2012

Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.7
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• pp.741-749
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• 2014

This paper proposes a machine vision module for PLCs (Programmable Logic Controllers). PLC is the industrial controller most widely used in factory automation system. However most of the machine vision systems are based on PC (Personal Computer). The machine vision system embedded in PLC is required to reduce the cost and improve the convenience of implementation. In this paper, we newly propose a machine vision module based on PLC. The image processing libraries are implemented and integrated with the PLC programming tool. In order to interface the libraries with ladder programming, the ladder instruction set was also designed for each vision library. By use of the developed system, PLC users can implement vision systems easily by ladder programming. The developed system was applied to sample inspection system to verify the performance. The experimental results show that the proposed system can reduce the cost of installing as well as increase the ease-of-implementation.

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.774-777
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• 2015

This paper introduces the world's first programmable video-processing platform for the enhancement of the video quality of the 8K(7680x4320) UHD(Ultra High Definition) TV operating up to 60 frames per second. In order to support required computing capacity and memory bandwidth, the proposed platform implemented several key features such as symmetric multi-cluster architecture for parallel data processing, a ring-data path between the clusters for data pipelining and hardware accelerators for computing filter operations. The proposed platform based on RP(Reconfigurable Processor) processes video quality enhancement algorithms and handles effectively new UHD broadcasting standards and display panels.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.171-176
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• 2001

This paper describes the methodology of an IEC 1131-3-based control logic generator for the control system design and converting algorithm between programmable languages. The proposed control logic generator is generated based on the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 1131-3 Standard. The generation method of object file was proposed on five programmable language based on IECI 131-3. The generation method of object file is represented as following; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using C code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ and MFC on MS-windows NT 4.0