• IE interfaces
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• v.16 no.2
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• pp.268-279
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• 2003

This paper presents critical steps in building client/server application with UML and Visual Basic, which are derived from the implementation case of a typical order processing system. To begin with, we briefly review the software architecture, the diagrams and the object-oriened building process in the UML. In the inception phase, it is critical to define the project charter, to draw use case diagrams, and to construct a preliminary architecture of the application. In the elaboration phase, it is critical to identify classes to be displayed in the class diagram, to develop user interface prototypes for each use case, to construct sequence diagram for each use case, and finally to design an implementation architecture. Steps to construct implementation architecture are given. In the construction phase, it is critical to design both the database and components. Steps to design these components are described in detail. Additionally the way to create the Internet interface is suggested.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• The Transactions of the Korea Information Processing Society
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• v.5 no.7
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• pp.1691-1716
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• 1998

본 논문에서는 계층적 블록매칭 알고리즘(HBMA)을 위한 두 가지 병렬 VLSI 아키텍쳐를 제안한다. HBMA는 계층에 따른 반복수행과 공간 인터폴레이션을 기반으로 수행되며, 이러한 수행 특성은 병렬처리의 장애요소인 데이터 종속성을 내재하고 있다. 제안된 아키텍쳐는 HBMA의 계층간 데이터 종속성을 해결하기 위하여 기본적으로 파이프라인 구조를 채택하고 있으며, HBMA에서 주어진 매개변수에 따라 세 단계의 스테이지로 구성된다. 제안된 아키텍쳐는 입력 프레임 데이터의 흐름을 제어하는 방식에 따라 두 가지 종류로 구분된다. U-Architecture는 단방향 스캔 순서를 따르도록 설계되었으며, B-Architecture는 양방향 스캔 수서를 따르도록 설계되었다. 각 아키텍쳐의 내부 메모리와 인터폴레이션 모듈은 해당 스캔 순서에 따라 동기적으로 동작할 수 있는 구조를 가진다. 성능분석의 결과로서 본 논문에서 제안한 두 가지 아키텍쳐가 모두 방송용 비디오 포맷을 실시간으로 처리할 수 있음을 보이고, HDTV 포맷은 가까운 장래의 VLSI 기술로 실시간 성능을 얻을 수 있음을 보였다. 또한, B-Architecture는 공간 연결성 내부 메모리 구조를 채택함으로써 입력 데이터의 재활용도를 높이고, 이에 따라 Q-Architecture에 비해서 데이터 입출력 핀의 개수를 약 반정도 줄일 수 있는 특성을 보이고 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Journal of Information Processing Systems
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• v.9 no.3
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• pp.425-434
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• 2013

In order for end-users in home networks to receive opportunities for useful services that go beyond legacy Internet Protocol TV (IPTV) services, this paper proposes a service platform that resides on the residential gateway (RG) for interworking between the home network and IPTV. This proposed service platform is called the home-oriented IPTV service platform (HISP) on the RG (HISP-RG). The proposed HISP-RG provides open architecture and functionalities to enable 3rd party IPTV service providers to locally and directly deliver home-oriented IPTV services to end-users in home networks. The HISP-RG can be an "add-on" and not a "built-in" solution for the existing standard RG. This paper introduces several home-oriented IPTV services that can be executed and delivered locally through the HISP-RG. Then, the open architecture and functionalities of the HISP-RG are defined and their requirements are specified. Finally, use cases of the HISP-RG for home-oriented IPTV services are presented.

• Journal of Information Processing Systems
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• v.14 no.5
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• pp.1286-1292
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• 2018

To support and protect firefighters in the scene of disaster, this research suggests an Internet of Things (IoT) system architecture that can be configurable and applicable to firefighting and rescue in various disaster situations. The proposed approach provides increased adaptability and reusability of systems compared to existing approaches. To validate the feasibility of the approach, a system of systems based on the architecture was developed and successfully tested for a specific firefighting and rescue scenario in a given test environment.

• Journal of Information Processing Systems
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• v.16 no.1
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• pp.42-48
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• 2020

This paper proposes an operating system architecture for unmanned aerial vehicle (UAV), which is secure against root exploit, resilient to connection loss resulting in the control loss, and able to utilize common applications used in Linux. The Linux-based UAVs are exposed to root exploit. On the other hand, the microkernel-based UAVs are not able to use the common applications utilized in Linux, even though which is secure against root exploit. For this reason, the proposed architecture uses a virtualized microkernel on the Linux operating system to isolate communication roles and prevent root exploit. As a result, the suggested Operating system is secure against root exploit and is able to utilize the common applications at the same time.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• Journal of Software Assessment and Valuation
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• v.17 no.2
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• pp.19-29
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• 2021

Blockchain technology fulfills the reliance requirement and is now entering a new stage of performance. However, the current blockchain technology has significant disadvantages in scalability and latency because of its architecture. Therefore, to adopt blockchain technology to real industry, we must overcome the performance issue by redesigning blockchain architecture. This paper introduces several element technologies and a novel blockchain architecture TPAC, that preserves blockchain's technical advantage but shows more stable and faster transaction processing performance and low latency.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.48-51
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• 2011

Universal Plug and Play (UPnP) is one of the most promising home network middleware technologies because of its straightforward implementation and zero configuration characteristics. However, it has a limitation of the operations only IP based network and proceeding in a single IP subnet. In this paper, we proposed network bridge architecture for UPnP network to interoperate heterogeneous network, UPnP and ZigBee. The proposed network bridge architecture is capable of configuration ZigBee device as a virtual UPnP device. This technique is promising for seamless inter-networking with ZigBee and UPnP network. Also, the architecture of the proposed network bridge architecture can be applied for a future smart home.