• Title/Summary/Keyword: processing architecture

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Design and Performance Evaluation of OBP Satellite B-ISDN Transport Network Architecture (OBP 탑재 n이성 B-ISDN 중계망 구조 설계 및 성능 평가)

  • Park, Seok-Cheon
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.3
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    • pp.901-908
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    • 2000
  • Satellite communication in the 21 century's high tech information world is developing rapidly, marked by high levels of applications and functions. For example, satellite communication can process and switch the speed of the service provided by a broad and vast digital multimedia system such as a long-distance all between nations or broadcasting transfer service, which is supplied by a contemporary satellite system. So, it bring about problems which lack of satellite orbit and gibes out frequency resource by increment of satellite universally. To support this, an OBP satellite system is need, which includes an on-board IF/RF switch, baseband signal processing, multi-beam antenna technology, as well as a simple transponder system. In this paper, we have outlined the next generation of satellite communication; satellite OBP transport network architecture, which offers multimedia service and applied frequency reuse method for multi-spot beam. The satellite B-ISDN transport network architecture is also analyzed.

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A Reliable Multicast Transfer Method Using Agent Sender & Receiver Concept (대리송수신자 개념을 이용한 신뢰성 있는 멀티캐스트 전송기법)

  • An, Byeong-Ho;Jo, Guk-Hyeon
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.2
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    • pp.396-407
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    • 1999
  • A Multicast transfer is a critical delivery method to provide a transport service to multipeer applications, the various problems on the multicast transfer environments have been occurred from the results of current research. One of these problems is the multicast transport service issue to guarantee reliability and scalability. First, this paper presents the related research of the reliable multicast transport methods, and then proposes a new transfer architecture using the Agent Sender and Receiver Concept(ASRC) to solve a reliable multicast transfer issue. we also propose a method to apply the proposed architecture(ASRC) to the well-known sender-initiated and receiver-initiated transport protocol. In order 새 validate the proposed ASRC architecture, t도 applied sender and receiver system si compared and analyzed over the processing requirement and maximum throughput.

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A Sharing Scheme for Connection Mamagement Objects in Different Distributed Processing Environments (이기종 분산처리환경상에서 연결관리 객체의 정보공유)

  • 신영석;오현주
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.4
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    • pp.793-803
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    • 1997
  • Open networking architecture is required to support new multimedia services as integrated functions of network management and service architecture. In this paper, we propose the methodology of building block modeling using object grouping concepts and the sharing scheme of different distributed processing environments based on open networking architecture. The building block has the functions of object management, security object instance registry and object mapping in object group. It is necessary for the connection management information to be shared on the interworking between two domains. We implemented and validated connection management functions using computational object modeling and building block modeling in different distributed processing environments.

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David II: A new architecture for parallel rendering processors with effective memory system (David II: 효과적인 메모리 시스템을 가지는 병렬 렌더링 프로세서)

  • Lee, Kil-Whan;Park, Woo-Chan;Kim, Il-San;Han, Tack-Don
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.05a
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    • pp.1655-1658
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    • 2004
  • Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture, called DAVID II, resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. The experimental results show that DAVID II achieves almost linear speedup at best case even in sixteen rasterizers.

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A Ring-Oriented Multicast Architecture over Mobile Ad Hoc Sensor networks

  • Yang, Yubai;Hong, Choong Seon
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.05a
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    • pp.1259-1262
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    • 2004
  • Detecting environmental hazards and monitoring remote terrain are among many sensor network applications. In case of fire detection, it is significantly valuable to monitor fire-spot's shape and trend in time. Mobile ad hoc sensor nodes right round are responsible for sensoring, processing and networking packets, or even launching extinguisher. In this paper, we proposed a ring-oriented Multicast architecture based on "Fisheye State Routing" (MFSR) to organize a group of mobile ad hoc sensor nodes in a multicast way. It is familiar with traditional mesh-based multicast protocol [1] in mobile ad hoc network, trying to concentrates on efficiency and robustness simultaneously. Certain applications-based solution for hazards is proposed, quantitative results including architecture and recovery algorithms of MFSR are also investigated in this paper.

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Pipelined Parallel Processing System for Image Processing (영상처리를 위한 Pipelined 병렬처리 시스템)

  • Lee, Hyung;Kim, Jong-Bae;Choi, Sung-Hyk;Park, Jong-Won
    • Journal of IKEEE
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    • v.4 no.2 s.7
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    • pp.212-224
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    • 2000
  • In this paper, a parallel processing system is proposed for improving the processing speed of image related applications. The proposed parallel processing system is fully synchronous SIMD computer with pipelined architecture and consists of processing elements and a multi-access memory system. The multi-access memory system is made up of memory modules and a memory controller, which consists of memory module selection module, data routing module, and address calculating and routing module, to perform parallel memory accesses with the variety of types: block, horizontal, and vertical access way. Morphological filter had been applied to verify the parallel processing system and resulted in faithful processing speed.

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