• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9A
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• pp.923-930
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• 2007

This paper presents MAPER, a media-aware power efficient routing algorithm over mobile ad hoc networks. Generally, multimedia services need various quality of service over the network according to their characteristics and applications. But it is not easy to guarantee quality of service over mobile ad hoc networks since the resources are very limited and time-varying. Furthermore only a limited power is available at mobile nodes, which makes the problem more challenging. Now, we propose an effective routing algorithm over mobile ad hoc networks that provides the stable end-to-end quality of service with the minimum total power consumption. Finally, experimental results are provided to show the performance of the proposed algorithm.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.3
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• pp.31-39
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• 2012

In this paper, we propose an energy-aware source routing protocol for maximizing a network lifetime in mobile ad hoc network environments. The proposed routing protocol is based on the source routing and chooses a path that maximize the path lifetime, by considering both transmit/receive power consumption and residual battery power in the mobile nodes from the perspective of source-destination end-to-end. This paper proposes a new routing cost and designs a new routing protocol for minimizing the control packet overhead occurred during the route discovery. Simulation results show that the proposed scheme has similar performances to the conventional routing schemes in terms of the number of transmission hops, transmission rate and total energy consumption, but achieves the performance improvement of 20 percent with respect to the lifetime.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.564-567
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• 2007

애드혹 네트워크는 무선 모바일 기기들만으로 구성 가능한 네트워크로서 무선 모바일기기의 특성상 제한된 에너지를 사용하게 된다. On-Demand 방식의 DSR(Dynamic Source Routing), PSR(Power-aware Source Routing)은 애드 혹 네트워크의 특성에 적합한 라우팅 프로토콜로 경로 탐색 시 브로드 캐스팅을 통해 단말기의 이동성과 전력 보유량을 고려하여 경로를 설정한다. 이러한 경로 탐색 기법은 네트워크를 구성하는 노드 수에 비례하여 경로 탐색시 소모되는 에너지 오버헤드가 증가하므로 대량의 노드들로 이루어진 애드혹 네트워크에서는 상당한 에너지 낭비를 초래한다. HPSR(Hierarchical Power-aware Source Routing)은 이러한 경로 탐색 오버헤드 문제를 보조경로를 이용해 감소 시켰지만, 초기 주 경로가 결정되는 시간에 보조경로 역시 동시에 결정 되는 특성을 가지고 있어, 경로를 이루는 노드의 에너지 정보가 시간적으로 낙후되고 실제 사용 시에는 에너지 효율이 낮은 경로가 되는 문제점이 발생한다. 본 논문에서는 노드들의 최신 에너지 정보로 부분 경로 설정을 함으로써 경로 탐색 오버헤드를 감소시킴과 동시에 변경된 경로의 에너지 효율도 최적화 시킬 수 있는 기법을 제안 한다.

• The Journal of the Korea Contents Association
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• v.7 no.1
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• pp.83-93
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• 2007

In this paper, we address a power-aware scheduling algorithm for a mixed real-time system which consists of periodic and sporadic tasks, each of which is characterized by its minimum period, worst-case execution requirement and deadline. We propose a dynamic voltage scaling algorithm called DVSMT(DVS for mixed tasks), which dynamically scales down the supplying voltage(and thus the frequency) using on-line distribution of the borrowed resources when jobs complete while still meeting their deadlines. With this scheme, we could reduce more energy consumption. As the proposed algorithm can be easily incorporated with RTOS(Real-Time Operating System), it is applicable for handhold devices and sensor network nodes that use a limited battery power. Simulation results show that DVSMT saves up 60% more than the existing algorithms both in the periodic-task and mixed-task systems.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.8
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• pp.343-348
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• 2013

We proposes a power-aware fixed-priority real-time scheduling algorithm for multimedia service, called static voltage scaling algorithm with multi-granularity resource reservation (STATIC-MULTIRSV). The multi-granularity resource reservation was introduced to deliver higher system utilization and better temporal isolation than the traditional approaches in [2]. Based on this, our STATIC-MULTIRSV is designed to reduce the power consumptions while guaranteeing that all I-frames of each video stream meet their deadlines. We implemented the proposed algorithm on top of ChronOS Real-time Linux [6]. We experimentally compared STATIC-MULTIRSV with other existing methods which showed that STATIC-MULTIRSV reduce power consumption by maximum 15% compared to its experimental counterparts.

• Nuclear Engineering and Technology
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• v.49 no.3
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• pp.484-494
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• 2017

In industrial plants such as nuclear power plants, system operations are performed by embedded controllers orchestrated by Supervisory Control and Data Acquisition (SCADA) software. A targeted attack (also termed a control aware attack) on the controller/SCADA software can lead a control system to operate in an unsafe mode or sometimes to complete shutdown of the plant. Such malware attacks can result in tremendous cost to the organization for recovery, cleanup, and maintenance activity. SCADA systems in operational mode generate huge log files. These files are useful in analysis of the plant behavior and diagnostics during an ongoing attack. However, they are bulky and difficult for manual inspection. Data mining techniques such as least squares approximation and computational methods can be used in the analysis of logs and to take proactive actions when required. This paper explores methodologies and algorithms so as to develop an effective monitoring scheme against control aware cyber attacks. It also explains soft computation techniques such as the computational geometric method and least squares approximation that can be effective in monitor design. This paper provides insights into diagnostic monitoring of its effectiveness by attack simulations on a four-tank model and using computation techniques to diagnose it. Cyber security of instrumentation and control systems used in nuclear power plants is of paramount importance and hence could be a possible target of such applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.397-404
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• 2012

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology considering thermal variation which contains buffer insertion with wire segmentation is proposed. Thermal aware LUT modeling for cell intrinsic delay is also proposed. Simulation results show the reduction of the worst delay after implementing thermal aware buffer insertion using by proposed wire segmentation up to 33% in contrast to the original buffer insertion. The error rates are measured by SPICE simulation results.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.185-193
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• 2010

In this paper, we Provide context-aware services based on UPnP Device Module including sensor unit in existing PLC network without additional infrastructure. so existing PLC devices are controlled based on knowledge context and can be used in a ubiquitous environment. And efficient remote control and device management based on UPnP can also be provided.

• Journal of Computing Science and Engineering
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• v.7 no.1
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• pp.30-43
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• 2013

Multicore and multiprocessor systems with dynamic voltage scaling architectures are being used as one of the solutions to satisfy the growing needs of high performance applications with low power constraints. An important aspect that has propelled this solution is effective task/application scheduling and mapping algorithms for multiprocessor systems. This work proposes an energy aware, offline, probability-based unified scheduling and mapping algorithm for multiprocessor systems, to minimize the number of processors used, maximize the utilization of the processors, and optimize the energy consumption of the multiprocessor system. The proposed algorithm is implemented, simulated and evaluated with synthetic task graphs, and compared with classical scheduling algorithms for the number of processors required, utilization of processors, and energy consumed by the processors for execution of the application task graphs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.