• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.7B
• /
• pp.1320-1325
• /
• 2000

A very simple and effective peak power reduction scheme for a downlink OFDM-CDMA system is proposed using the relationship between peak-to-average power ratio (PAPR) and out-of-phase autocorrelation. Since power spectrum and autocorrelation function are Fourier transform pair, the PAPR property of the sequences can be estimated by the out-of-phase autocorrelation function of the spreading sequences. Thus, by scrambling the spread data in the frequency domain, we can reduce the sidelobe energy of autocorrelation, and at last, suppress PAPR in the proposed OFDM-CDMA system.

• Proceedings of the IEEK Conference
• /
• 2002.06e
• /
• pp.67-70
• /
• 2002

In this paper, we have researched a Automatic Power Factor Correction and THD reduction System for the multiple connection of CFL. Also in this paper, the power factor has been researched for the design of CFL, found the reason why the power factor is low and THD is too high. This paper has designed the PFC System for the multiple connection of CFL, and then we have increased the power factor and reduced the total harmonic distortion, by implementing them.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.6
• /
• pp.474-480
• /
• 2001

In this paper a low signal reduction communication system that does not use the communication line but power line is presented It will be very useful for an information-oriented society with tele-metering and home automation. The conventional system has a difficulty in transmitting information due to decreasing communication voltage. The proposed system employs a special type switching amplifier system which has a low inner resistance and uses high efficient ferrite core in coupling circuit. This new system is proposed to reduce the loss of conductor load and coupling circuit in a PLC system.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.30 no.3 s.246
• /
• pp.193-200
• /
• 2006

The purpose of this study is to compare the part-load performance of a SOFC/GT hybrid power system with three different kinds of load-following operation modes. The primary mode for the part load operation of a hybrid power system is the reduction of supplied fuel (e.g., fuel control mode) to the hybrid system. The other two options, i.e., variable speed and VIGV controls, are related to the reduction of supplied air simultaneously with the reduction of supplied fuel to the system. With the performance analysis of a SOFC/GT hybrid power system, it is concluded that the variable speed con佐ol mode Provides the best performance for the part-load operations. It is also found that the VIGV control mode, with its better performance behavior than the fuel control mode, can be used as an important option for the part-load operation especially in case that the variable speed control mode can not be adopted.

• Proceedings of the KIEE Conference
• /
• 2006.04b
• /
• pp.57-61
• /
• 2006

In the single-phase switched reluctance motor (SRM) drive, the required DC source is generally supplied by the circuit consisting of bridge rectifier and large filter capacitor connected with DC line terminal. Due to the large capacity of the capacitor, the charged time of capacitor is very short from the AC source. Lead to the bridge rectifiers draws pulsating current from the AC source side, which results in reduction of power factor and low system efficiency. Therefore a novel single-phase SRM drive system is presented in this paper, which includes drive circuit realizing reduction of torque ripple and improvement of power factor with a novel switching topology. The proposed drive circuit consists of one switching part and diode, which can separate the output of AC/DC rectifier from the large capacitor and supply power to SRM alternately, in order to realize the torque ripple reduction and power factor improvement through the switching scheme. In addition, the validity of the proposed method is tested by some simulations and experiments.

• Proceedings of the KIEE Conference
• /
• 2006.11a
• /
• pp.161-163
• /
• 2006

This paper introduce the technology of peak demand reduction using automatic water tank pumping system on the apartment. That systems on the apartments installed water tank can control pumping(electricity) demand. Generally, system peak demand is occurred at the same time on workday and many water pumps consume electric power randomly. At this point, shift of operating time of water pump can reduce peak demand using automatic water tank pumping system. We were operating this system on some apartments for test of effect of peak demand reduction. and we represent result of demand shift. This result suggests that spread of the automatic water pumping system can contribute to reduce system peak demand and reduce system operation cost.

• The Magazine of the IEIE
• /
• v.25 no.5
• /
• pp.31-41
• /
• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.66 no.1
• /
• pp.7-14
• /
• 2017

Recently, the power consumption of industrial consumer has increased rapidly, causing problems such as lack of power reserve margin in summer and winter, and therefore there is a growing need for maximum demand power management to consumers. In this paper, we studied small microgrid system consisting of battery ESS and photovoltaic power system, applied to small and medium sized factories to reduce the maximum demand power of daily industrial power load. To verify the validity of the study, we simulated a small microgrid system using Matlab/Simulink software. As a result of applying the simulation to small and medium sized plants that consume a lot of power, it is confirmed that there is a 13% reduction in demand compared to the existing maximum demand power. This result is expected to contribute to the improvement of the power reserve margin.

• ETRI Journal
• /
• v.29 no.3
• /
• pp.402-404
• /
• 2007

One of the major disadvantages of the orthogonal frequency division multiplexing system is high peak-to-average power ratio (PAPR). Selected mapping (SLM) is an efficient distortionless PAPR reduction scheme which selects the minimum PAPR sequence from a group of independent phase rotated sequences. However, the SLM requires explicit side information and a large number of IFFT operations. In this letter we investigate a novel PAPR reduction method based on the radial basis function network and SLM.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.29 no.10
• /
• pp.89-96
• /
• 2015

Explicit numerical integration methods for power system transient stability simulation require very small time steps to avoid numerical instability. The EXST1 exciter model is a primary source of fast dynamics in power system transients. In case of the EXST1, the required small integration time step for entire system simulation increases the computational demands in terms of running time and storage. This paper presents a practical exciter model reduction approach which allows the increase of the required step size and thus the method can decrease the computational demands. The fast dynamics in the original EXST1 are eliminated in the reduced exciter model. The use of a larger time step improves the computational efficiency. This paper describes the way to eliminate the fast dynamics from the original exciter model based on linear system theory. In order to validate the performance of the proposed method, case studies with the GSO-37 bus system are provided. Comparisons between the original and reduced models are made in simulation accuracy and critical clearing time.