• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.257-263
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• 2002

Test scheduling of SoC becomes more important because it is one of the prime methods to minimize the testing time under limited power consumption of SoCs. In this paper, a heuristic algorithm, in which test resources are selected for groups and arranged based on the size of product of power dissipation and test time together with total power consumption in core-based SoCs is proposed. We select test resource groups which has maximum power consumption but does not exceed the constrained power consumption and make the testing time slot of resources in the test resource group to be aligned at the initial position to minimize the idle test time of test resources.

• Proceedings of the Korean Nuclear Society Conference
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• 1998.05a
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• pp.398-403
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• 1998

The Load Rejection to House Load test at 50% power was successfully peformed during the UCN 3 PAT period. In this test, all plant control systems automatically controlled the plant from 50% power to house load operation mode. The KISPAC code, which was used in the performance analysis during the design process of UCN 3&4, predictions of the test agreed with the measured data demonstrating the validity of the code as well as the completeness of the plant design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.188-196
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• 2005

This paper presents a new test data compression and low power scan test method that can reduce test time and power consumption. A proposed method can reduce the scan-in power and test data volume using a modified scan cell reordering algorithm and hybrid adaptive encoding method. Hybrid test data compression method uses adaptively the Golomb codes and run-length codes according to length of runs in test data, which can reduce efficiently the test data volume compare to previous method. We apply a scan cell reordering technique to minimize the column hamming distance in scan vectors, which can reduce the scan-in power consumption and test data. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases. The proposed method showed an about a 17%-26% better compression ratio, 8%-22% better average power consumption and 13%-60% better peak power consumption than that of previous method.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1107-1113
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• 2015

Test temperature is an important factor affecting the measurement results of dielectric response of field power transformers. In order to better apply the polarization and depolarization current (PDC) to the condition monitoring of oil-paper insulation system in power transformers, the influences and elimination method of test temperature on PDC characteristic spectroscopy (PDC-CS) were investigated. Firstly, the experimental winding sample was measured by PDC method at different test temperatures, then the PDC-CS was obtained from the measurement results and its changing rules were discussed, which show that the PDC-CS appears a horizontal mobility with the rise of temperature. Based on the rules, the “time temperature shift technique” was introduced to eliminate the influence of test temperature. It is shown that the PDC-CS at different test temperatures can be converted to the same reference temperature coincident with each other.

• Journal of Digital Contents Society
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• v.9 no.3
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• pp.471-481
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• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• Journal of the Korean Data and Information Science Society
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• v.16 no.3
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• pp.609-620
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• 2005

In the secondary data analysis for categorical data, situations often arise in which the estimated cell variances are available, but not the full matrix of variances. In this case researchers are often inclined to use Pearson-type test statistics for homogeneity. However, for a complex sample observed cell proportions are not distributed as multinomial and Pearson-type test statistic generally is not distributed asymptotically as chi-square distribution. This paper evaluates powers for Wald test and Pearson-type test and the first order corrected test of Pearson-type test for homogeneity. The resulting power curves indicate that as the misspecification effect increases, the amount of inflation of significance level and the loss of power Pearson-type test are getting more severe.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1348-1349
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• 2011

In this paper, The case of power performance test for 3MW wind-turbine system is introduced. For the verification of power curve and the certification of wind-turbine, power performance test is very important. This paper described the power testing results of a 3MW wind turbine and analysed an uncertainty about the testing. The measured power curves are very closely coincide with the calculated. Total uncertainty of measured data for Power Curve is 120~200kW in the rated power.

• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.59-62
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• 2002

Before a developed digital Power System Stabilizer(PSS) is installed to real power system, an efficient trial test for installing PSS is needed. In this paper, the performance of developed digital PSS for a single hydro-turbine generator and infinite bus system has been investigated using Real Time Digital Simulator(RTDS) in order to install PSS to real power system practically. The test system was composed of RTDS, three phase voltage/current amplifier and the PSS and the test scheme provided a very efficient way to verify the design and control performance of a PSS to be applied to real power system. The trial installation test through AVR 3% step test and three fault analysis may be guaranteed to install PSS to real power system.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.35.2-35.2
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• 2011

A wind turbine power performance test is very important to wind turbine manufacturers because a wind farm developer or planner must want to define power performance characteristics and reliability of new wind turbines. Based on the IEC 61400-12-1, A wind turbine test site has to be nicely installed at flat terrain for testing. We are developing the wind power system which is IEC wind class IIa model with rated power of 3MW. KEPCO's Gochang power testing center was considered as candidates to build the test site without site calibration. This paper aims to verify the validity of the test site by using implement site assessment result that was based on IEC 61400-12-1.